higher PFD freq,slower locking time?
时间：04-08
整理：3721RD
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Hi everyone,
I have met a problem on PLL lock time. I found that the PLL with 10MHz PFD
freq has a great smaller lock time than a PLL with 30MHzPFD,although they have
the same loop band width and phase margine. this is an experiment
measurement resault.
I once use the ADIsimpll to confirm the resault. The simulation shows a PLL
with 10MHz PFD freq,50kHz LBW, 48 PM, indeed has a smaller settling time than
the PLL with 30MHz PFD freq,50kHz LBW, 48 PM!
The ADI app said the higher PFD freq,the faster locking time, is that wrong?
Added after 41 minutes:
I also use the national's easyPLL to simulate the
PLL lock time. The resualt is the same . in 500MHz
span, 10MHzPFD is 78us, while 30MHz PFD is 220us.
I have met a problem on PLL lock time. I found that the PLL with 10MHz PFD
freq has a great smaller lock time than a PLL with 30MHzPFD,although they have
the same loop band width and phase margine. this is an experiment
measurement resault.
I once use the ADIsimpll to confirm the resault. The simulation shows a PLL
with 10MHz PFD freq,50kHz LBW, 48 PM, indeed has a smaller settling time than
the PLL with 30MHz PFD freq,50kHz LBW, 48 PM!
The ADI app said the higher PFD freq,the faster locking time, is that wrong?
Added after 41 minutes:
I also use the national's easyPLL to simulate the
PLL lock time. The resualt is the same . in 500MHz
span, 10MHzPFD is 78us, while 30MHz PFD is 220us.