Rejection at PFD frequency beside VCO output carrier(PLL debug)

Hi all,

I used ADF4360-7 in my PCB, and found one issue on rejection,please you kindly advise.

Reference OSC is 10MHz,PFD frequency is 200KHz,Loop bandwidth is 10KHz. When I set the output carrier is 900MHz,the rejection at +/-900.2MHz is about -75dBc and can be accepted. But when i set the carrier is 900.2MHz,the rejection at +/-900.4MHz decreased to only -41dBc.
I tried and found,the rejection at +/-PFD is ok when VCO outputs integrate carrier(840MHz/900MHz/960MHz) and is very bad when VCO outputs decimal carrier(900.2MHz,900.4MHz,900.6MHz). I have tried and modified the Loop bandwidth from 20KHz to 10KHz and 5KHz, but no improvement. I think it's not related to loop bandwidth.

Thanks!

I presume that it's not an intrinsic problem of the ADF4360 chip, because ADI's specification are usually trustworthy. But we can't be sure because the PFD spurs are only specified for an integer VCO to REF frequency ratio in the datasheet. I imagine that insufficient chip grounding and bypassing can bring up the problem. At non-integer frequency ratios, reference and VCO frequency can create intermodulation products that may enter the VCO control loop, causing the spurs.

Thanks to FvM.

I finally found that OSC outside has an effect on the PDF spurs, the output reference voltage affects it. I add one serial 3K resistor between the OSC output and PLL input to decrease the reference OSC level and then,the spurs dcreased too.

First: Does the VCO operate at only 840MHz, 900MHz, and 960MHz,. Or does it
operate FROM 840 - 960 MHz ?

2nd: Do you have a plot of the Spectrum ? Like a Phase noise plot would be best.
It will be good to know if this is a Spur at 900.4MHz or does the whole spectrum increase.

One could be that you are operating the VCO Beyond it's limit, and the Other could be that
you are getting a Mixing product that passes a strong signal (Spur) .

840~960MHz is the whole operation frequency and the all the spurs like +/-900.4,+/-900.6,+/-900.8......are increased.

It's still in the VCO limit.

thanks.

Hi.
I think the bypass capacitors in reference path and power supply of pfd and ref. div may help you.