Can fractional spur be really removed? help!

Hello everyone:

Recently,I have tried to make a frac-N PLL for 1G~2G. I used the ADF4156 and ADF4157,which's datasheet says that the fractional spur could be removed by delta-sigma and dither.
But in my circuits,both chips all have strong fractional spurs. that means if the FRAC register is set to 0, all work very well, low phase noise, no spurs. But if the FRAC is not 0 ,the spurs appear.
In ADF4156 ,the spur appears at 1/MOD*fPFD offset. In ADF4157 ,the spur appears at FRAC/MOD*fPFD offset.
I have tried to change the loop filter,PFD freq,output freq,etc. Nothing works.
I begin to doubt if the chip really could remove frac spurs.

Anyone have used the simillar fractional N PLL?
could anyone give me some suggestion?

my PLL spec are: fPFD 30MHz,loop width 50kHz ,phase margin 45,freq step 10kHz

could anyone help me?

i want to know why do that too。。。

I take it that you have enabled the dithering option, by choosing 'lowest noise AND spurs' mode of the ADF4153. You may get better results by decreasing the loop BW, since the fractional spurs are an in-band artefact, other system requirements permitting ofcourse. For instance, you will end up with higher integrated phase noise, since at such high phase detector frequency, typically in-band noise will be low compared to the VCOs' phase-noise.
Another technique involves placing a notch, usually effected by a series LC network, in your loop filter, but stability will need attention. Higher order loop filters are sometimes used, but their design is not trivial, especially as they are not covered by tools such as ADiSimPLL. Such designs can be found in high performance testing gear, such as spectrum analyser local oscillators.
At a more abstract level, engineering is a science of compromise; considering the high fractionality and relatively wide LBW, are you perhaps asking too much from a simple single-loop PLL?