Can sp.file accurately do the time-domain simulation in on-chip balun design?
时间：04-08
整理：3721RD
点击：
Hi guys
I'm now designing a on-chip balun. two methods may be adopted.
First, get sp. file from momentum simulation,and use this sp.file to embedded in the rest of circuit do the full simulation such as dc ac noise tran pss ect.
Second, to model RLCK use it to simulate instead balun.
what puzzled me is: can sp.file accurately do the time-domain simulation while RLCK model is so complex and hard to prefigure.what should I choose?
I'm now designing a on-chip balun. two methods may be adopted.
First, get sp. file from momentum simulation,and use this sp.file to embedded in the rest of circuit do the full simulation such as dc ac noise tran pss ect.
Second, to model RLCK use it to simulate instead balun.
what puzzled me is: can sp.file accurately do the time-domain simulation while RLCK model is so complex and hard to prefigure.what should I choose?
Hi, microwaver.
My little experience show me that .sp file is unsuitable for time domain simulations in Cadence ADE. Even for small-signal simulations i had to use coupling capacitors to isolate my nport block for the dc currents and voltages were correct. But you cab use broadband spice model generator in ADS to create .scs model for transient and pss analyses.