How to model bias network accurately?

Hi all,

I am doing a LNA deisgn. Part of the requirement for the project is to model the DC bias network accurately. (To check if the bias network keeps RF from going off-chip.)

I am not sure where to start. Does anyone have an idea? Or recommend any related paper as reference?

Thanks.

"To model the DC bias..." sounds nothing to me.If you meant " proper biasing an LNA", OK.
If you have already known how to design an LNA, you have already learnt how to design a proper DC bias.
You question is too floating..

I did design a DC bias for my LNA. I guess I want to check and make sure no RF signal is leaking off-chip. maybe by doing EM simulation on PCB?

EM simulation can be done with a realistic Package Model that has also been simulated in a 3D EM simulator.
But the best one is to try on a PCB because simulations don't give all.

Do the Co-simulation with your PCB and DC bias layout 3D simulation.

to properly model a bias network, you just need great care in the details of the model used. Like if there is a series inducor, model its q accurately. If it has a shunt capacitor, model the capacitor's series resistance, and mounting inductance (like via hole inductances) VERY accurately. If it is at very high frequency, you ight need an electromagnetic simulator to model the free space propagation OVER the series inductance. Try to pick an inductor that has a details S parameter file from the manufacturer, to properly simulate leakage above the series resonant frequency SRF--there is often an engineering tradeoff between getting the high series inductance you want and the SRF frequency being way above your operating frequency. SRF is the frequency where your "inductor" stops acting electrically like it is an inductor.

If you screw up the details, like forgetting the via hole inductances, you answer can be off 20 dB or so for isolation.

One error that you can explain away is that to analyze a bias network on an analysis program, you will be terminating the RF output with 50 ohms, and the input and DC port will be connected to a 50 ohm characteristic impedance. BUT in real life your power supply will NOT look anything like a 50 ohm resistive load. So the predicted isolation will be technically a little off.