buffer design for VCO in TSMC 0.18u

I have a VCO with Vp-p = 1.9 in .18u TSMC process. my freq is from 450M to 900M.
iwant to design a buffer for my VCO. Can anybody help me?

A CMOS differential pair with current source and then Source follower with current source will serve you..
Differential pair will have high input impedance that wil not load your VCO, Source follower wil have low output impedance to drive low loads.

As i mentioned above, i have a large output swing in high freq and lower swing in low freq. this swing will put the buffer stage into triode or off. so i have to lower the output swing by use of capacitive divider.
The output load is 50ohm.
now what is your idea?