How to design UWB Multipler with maximum outputgain

Can any one suggest me how to design & which multiplier is adopted to get Max. gain for UWB application

please explain exactly what you mean when you say "ultrawidband multiplier" and "gain"

Actually I wan to design a multiplier in 0.18um CMOS technology for UWB receiver means multiplier should have 3-10GHz bandwidth with max gain but without using inductor. Overally It should have max . senstivity and linearity and output should be in form of voltage . Then how I start design of this multiplier means which parameter I have to take as refence ,then design MOS can be done .

My question is, do you mean you want an ultrawideband frequency multiplier? Like you put in 1.5 to 5 GHz and want 3 to 10 Ghz to come out?

I would think that the way to do that would either to have an active gate that took a pulse and outputed a narrower pulse, or you had a non-linear transmission line that sharpened the input pulse (like a soliton generator)