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Help me construct a Costas Loop to demodulate a 1.1 GHz DPSK signal

时间:04-07 整理:3721RD 点击:
Greetings all,

I have been lazily working on a PSK demodulator for ADS-B (Automatic dependent surveillance-broadcast) for a couple months (on and off). However, i have gotten to the point that I need some help. I have a BSEE, but it is mostly in the FPGA/embedded realm; not as much in the RF.

I am trying to construct a Costas Loop (analog, not a DSP project) to demodulate the 1090MHz DPSK signal.

right now my design is a costas loop:
Antenna > SAW filter > LNA (20db) > LT5575 I/Q mixer > BPF > mixer (maybe LT5511) > Loop Filter > VCO > back to LO input of LT5575.

it would basically look like this but with a SAW filter and LNA up front:



here is what I plan to use for my loop filter (input to VCO is on the right):


with values:
C1:68pF
C2:470pF
C3:1.5pF
R1:309ohm
R2:100ohm

my questions are:
1. is that loop filter going to work? bit rate should be 1Mbit/s with a DPSK modulation scheme. how sensitive is the loop filter? can anyone give me a resources for quickly estimating the loop filter values I need?
(yes that was more than 1 question, but they are all in the same category :P)

2. can someone give me a rundown of IP2 and IP3? i am not sure what effect these things will have on my design.

3. are there any simple methods for protecting the front end of my receiver, in case I accidentally take a close-range transmission?

4. Do you have any suggestions for improving/altering my design? I would appreciate it.

5. are there any software program that I can use to simulate the circuit (with mixers and all)? I am a little unsure what out "demodulated binary output" (the branch of the Costas Loop) will look like as the circuit goes through the lock process.

thank you very much

Analog Devices : Forms : ADIsimPLL Version 3.3 Request for Software (good for designing PLL,...)

and

Switchercad => Linear Technology - Design Simulation and Device Models

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