[Help] error on simulation about verilogA block

Hi. I am new to Cadence IC5141. I am doing a simple simulation. I use Cadence IC5141 on RHEL5.4.
I use model writer to write a delay cell, the verilogA code is listed here:

"
`include "discipline.h"
`include "constants.h"

module delay_elem (vin, vout);
input vin;
output vout;
electrical vin, vout;

parameter real td = 1.0n from (0:inf);

analog begin
V(vout) <+ absdelay(V(vin), td );
end
endmodule
"

And I use a pulse source from analogLib to give this delay cell pulses. And the delay cell is connected to a 50ohm resistor. I use the ADE (spectre) to simulate the cell.

I chose tran analysis.

However, there is error here:

Error found by spectre during circuit read-in.
"input.scs " 9 :Top-level parameter 'm' must be initialized with a value or expresstion.
Warning from spectre during circuit read-in.
"input.scs" 10: parameter name 'm' is researved for the subcircuit multiplicity factor. So a formal parameter of that name is ignored.

Error found by spectre during circuit read-in.
"input.scs" 16 : statementis not in spectre format.
Warning from spectre during AHDL read-in.
"/home/zxr/circuit_design/MyResearch/delay_1ns/veriloga/veriloga.va", line 28: warning: `(abs)delay()' dose not account for phase shift in small-signal analysis.


My question is about the variable m. I never set the variable m. And I didnot describe it in the delay cell.

Can anyone help me?

There is no simulator whose name is "Cadence IC5141".
"Cadence IC5141" is a name of Design Framework where you can use many simulator engine such as Synopsys HSPICE, Agilent ADSsim, Agilent GoldenGate, Cadence Spectre, etc.

It seems that you use Cadence Spectre in IC5141.
Show me "input.scs".