Ku-band PLL Architecture: Prescalars or Multipliers

I am planning for two architectures-

1> working in low freq and using a doubler(×2) at the final output
2>using a divide-by-two(÷2) prescalar at the feedback after the vco

In which architecture phase noise will be LESS?

Also please see the attached document.It is an application note from Hittite.It says that using a prescalar actually IMPROVES the phase noise while a multiplier degrades it.Prescaling is same as dividing the frequency right?...so why we read in books that setting a higher value of N degrades the phase noise by 20logN?

Thanks :)

Close to carrier phase noise will be similar. Phase noise at offsets behind PLL BW will be different because of VCO's with lower output frequensies have PN more than 6 dB lower. Perhaps PLL BW will be 100-500 kHz in your design. If your interests are up-to 100-500 kHz suggest don't use frequency multiplier (1st variant). Otherwise additionaly you have to design it.