how to design clock recovery circuits for the ASK demodulator?

hi :)

I have to design a clock recovery circuit in the ASK demodulator in the passive tag.

Any modulatation index will be fine. But, the 100% ASK modulation index signals should be problem.

How to recover the clocks from the 100% ASK moulation signals?

Thanks.

If the problem is related to 13.56 MHz RFID, all processing (for receive and send) has to be done synchronous to the carrier frequency. So for 100% ASK (e.g. ISO 14443 type A), a PLL locking to the carrier would be a solution.

You mean using the PLL locking with the carrier signal(13.56MHz)? In 100% ASK signals, the zero section never have carrier signal.
How can I use PLL locking with the zero section? Is it possible?

If designed suitably, the PLL will continue the carrier phase across the zero (< 3 us) with sufficient accuracy. Actually I don't know, how various tag designs manage this problem. But the protocol specification effectively requires to "count" carrier cycles to time the tag response, so a PLL would be obviously a straightforward solution.