Help me design a CMOS LNA with 4dB gain of noise figure
I need to design a CMOS LNA (0.18 micron technology) with a gain of Noise figure of about 4dB and a gain of about 15dB. I just wanted tour opinion as to how to start, and what architectures I should look at.
Cascode structure can be a good starting point but if your frequency is very high you should also consider single ended cascade configuration.
My frequency is 4.1 GHz...I am planning to use a single ended LNA with common source inductive degeneration..
Also I have a problem in grasping what exactly Rg stands for in some of the small signal models...Is it the gate resistance or some parasitic resistance...If so how do we calculate it...
Thanks..
If it is part of a larger IC, good luck .
If it is just an LNA IC, waste of money for inferior performance.
At 4.1 GHz, using 0.18 process may create a little bit disappointment but it's worthy to try..
But If I were you, I use GaAs process at those frequencies because even you obtain NF with 0.18, gain will probably low than you expected.
Rg is distributed Gate resistance along gate and it's main contributor into NF performance of an LNA.It may be calculated if you know Rsheet value of your process.But if you consider the Gate strip as a transmission line, there will be some fringed capacitors between Source and Drain contacts.Therefore you should extract your layout and then look at impedance value of gate..
How can you make an LNA using CMOS? For one thing, CMOS is generally run in saturation, and for another it is nowhere near fast enough.
Just about every recent model cellphone is all CMOS RF frontend.
Thanks for your reply guys....
I was wondering if the common source regenerative method would work here, or would I have to try cascode....
Also is there any resource where I can find a step-by-step tutorial for cascode LNA design...