微波EDA网,见证研发工程师的成长!
首页 > 研发问答 > 微波和射频技术 > 天线设计和射频技术 > oscillations in range of 50MHz-1GHz in 3.1-3.5GHz Power amplifier

oscillations in range of 50MHz-1GHz in 3.1-3.5GHz Power amplifier

时间:04-07 整理:3721RD 点击:
I Have Got Oscillations in range of 50MHz-1GHz in my 3.1-3.5GHz 120W Power Amplifier. The dreiver for 120W PA is 20W and 1W amplifier.
But How to stop the oscillations in lower frequency range.

Avoiding ground loops by securing input and ouput terminals and isolating power supply will solve the problem. Try differnt power supplies for each section.

These are out of band oscillations. You are probably using mosfet devices. These show very high power gain at low frequencies, so relative small feedback (within a stage or across stages) may provoke oscillation (and destroy your active devices).

Probably the load and source impedance as seen by the active devices are such that oscillation can occur (this happens offen in mosfet amplifiers). Mostly this is solved by assuring that drain and or gate sees sufficient Real part for the out of band frequencies. You may check application notes from the device manufacturer.

As you are using a multi-stage design, use Alertlinks approach to rule out any power supply feedback across the stages. If this is not possible, you should see a change when modifying the power supply decoupling.

1)Thank you for reply WimRFP, Could you please suggest Any passive components with value to make drain or gate sees sufficient Real part for the out of band frequencies?
2)What is meant by alertlinks approach?
Thanks in advance

If the power supply for each stage isn't decoupled well, some RF power may reach the input of the low power stage(s) and this may cause oscillation. You probably optimized power supply decoupling for the intended frequency band. Sometimes people forget to look to the bahavior at out of band frequencies. If you feed from separate supplies, you may notice a difference. If so, there may be a feedback path via the power supply network (on your PCB).

Regarding gate/drain termination for out of band frequencies, this is mostly done by resistors in the bias circuit that are (partly) bypassed for the intended frequency (so they don't dissipate significant in-band power). Also resistive feedback from drain to source is used to reduce the gain at low frequency, but I don't know whether this is used with todays devices at 3 GHz.

Did you check the manufacturers application data and similar data from other brands (microsemi, freescale, NXP, ST-microelectronics, etc?

1Thank you for reply WimRFP
iam using the same pcb layout mentioned in nxp data sheet, but still am geeting it.
2)What is meant by alertlinks approach?

---------- Post added at 21:27 ---------- Previous post was at 21:21 ----------

http://www.nxp.com/documents/data_sh...G3135S-120.pdf
http://www.nxp.com/documents/data_sh...6G3135S-20.pdf

i have used same layout specified

You are making a multi stage design, so the layout can't be the same (I see only one transistor in each layout). The layout in the datasheets are just parts of your layout.

The presented NXP layout is to show what the device can do (in that layout). The load is very likely wide band 50 ohms and the source impedance will also have low VSWR. This is frequently done by inserting a 3 dB attenuator between source and input of the PA. This assures a VSWR < 3 as seen from the input of the amplifier towards the source (wide band).

In your case the driver will show bad VSWR to the input of the final PA, especially when outside the intended frequency range. The input matching of the PA and the output matching of driver together, may show strange (resonating) behavior. Do you have any possibility to test the stages separately? If so, can you add an attenuator in between?

Looking to out of band frequencies (below operating frequency) of the NXP layout, you can see that for low frequency, the base sees a 50 resistor (in parallel with lumped and trace capacitances). However when the input series capacitor will resonate this may result in a low reactive impedance seen from the gate of the final PA transistor.

Other thing can be the mounting of the PCB to the heatsink (insufficient bolts or bad contact) and number vias to ground.

Maybe Alertlinks can comment on his point, but the actions are to avoid/figure out that you have low frequency RF feedback via the power supply or common ground paths. This can occur (from experience) and may result in long lasting headache.

Maybe you can try to add isolator between stages, to improve VSWR, and may stop OSCILATIONs.

try using ferrite beads on PA supply and also on driver power supply.

Copyright © 2017-2020 微波EDA网 版权所有

网站地图

Top