CMOS LNA 1dB compression point

Hello,
I am designing an 30-50GHz CMOS LNA. I have simulate all the necesary parameters except the 1dB compression point and the IIP3.

I am using Cadance Virtuoso. Can somebody explain to me how to simulate these two points. I have found some manuals online but they are all for narrow band LNAs. I would really appreciate if someone could explain to me how to set this up.

thanks

Narrowband or Wideband.. No matter, simulation technique is same for both.
You will select frequency points in your band and you should do P1dB at those points and collect the data and plot P1dB vs. frequency.
For OIP3, you will select frequency pairs in your band and do you OIP3 simulation for each pairs and then draw OIP3 vs. frequency plot...

hi, which transistor model do you use. I am tryring to design 400MHz LNA and I am using nmos transistor from PRIMLIB library (is this ok)