LNA Design

Hello! i am designing an LNA on cadence.Can anybody tel me how shall i start the practical work..I have studied a lot of related topics i mean background is clear.But i dont know how to implemnt and where to start

Best place to start is probably picking a transistor with good characteristics at your operating frequency.

-Select Architecture
-Select the biasing in according with noise and nonlinearity
-Select the transistor sizes regarding to bias curents
-Do the simulations
-Do the layout
-Do the optimization
and finally repeat the design stepts until you find the optimum circuit..

Hi
I have to design an LNA at 900MHz on cadence. I m using tsmc 0.35nm technology file. The transistor I have selected for my application is Avago technologies ATF-34143. But this transistor is not available in cadence. In cadence tsmc library I only have nch transistor and nch5 transistor. The only thing of the transistor I can change is the W and L. my first question is how to bring the selected transistor in cadence?

Secondly I have taken start from the Thomas lee book The Design of CMOS RFIC. This book has explained the noise models of MOS and the methods to optimize it but I am confused because if I use this optimization these are related to fabrication process and it is not in my hand the only thing in my hand is to optimize the transistor using external loadings like resistor, capacitors and inductors. So I cant do the noise optimization. Am I right?
If I m wrong please guide me in the right direction.
Thanks in advance

I was thinking that the designing and optimization given in the Gonzalez should be followed by me. M I right?