Design of microstrip TLs with Zo = 50 Ohms
I am connecting an FPGA to a DDR3 memory, and there are some constraints on the traces as follows:
- Traces should be 3 inches or less.
- Trace widths should be 3 to 5 Mils.
- Trace Spacing should be 3 times trace width.
- Spacing between Differential traces is 20 Mils.
When I use wcalc to calculate the characteristic impedance of the lines, It never become below 136 Ohms!, My target is 50 Ohms, how can I achieve it in the presence of these constraints ?
I'm gonna use a 4-Layer FR4 PCB + the frequency is around 500MHz.
Hello,
Can you reduce the distance between the ground layer and the trace layer? If so, this will result in lower Zo, reducing the distance beetween ground plane and traces also reduces crosstalk.
Do you realy need always 50 Ohms for DDR3 (I am not a specialist in DDR3)?
I tried to reduce the distance, but can't reach lower than 136 Ohms!
hmmm, I don't know, I read that most devices have Zo=50 Ohms, I will do some research about DDR3 Zo.
Any other tips will be much appreciated.
Thanks.
What is the distance between signal layer and ground?
50 ohms matching is generally OK for SSTL IO-standards, but you should be able to change the impedance matching. It's adjustable
at least on the RAM side, for the controller, depends on the device.
I can't reproduce your assumed 136 ohms, I get around 100 ohm single ended for a standard 4-layer PCB stack and 5 mil trace.
But it's actually impossible to achieve 50 ohm on a 4-layer-PCB with a trace width suitable for digital routing. Typical computer
boards have much more layers and respectively smaller trace width.
Hello,
I also though that you can get the RAM side at about 120 Ohms for DDR3 (but I am not into this matter).
The reason for asking for the layer height is that my data also shows around 100 Ohms, so maybe he is doing something strange in his Z0 calculation.
15.5mil .. Calculated by dividing the standard 62mil of the whole PCB thickness by the number of required layers (4-Layer PCB).
These are wcalc calculations for my inputs, I corrected a simple error in the input and the impedance is now ~105 Ohms.
Hello, thanks for help! :)
How can the number of layers affect Zo ?
The inputs to calculate Zo are:
- Length of trace.
- Width of trace.
- Substrate thickness. (Increasing the layers will decrease the thickness, but it does not greatly impact the calculation of Zo)
- Dielectric constant.
Am I missing something here ?
Added after 7 minutes:
P.S.
Decreasing the height of substrate to 3mils makes Zo = 52 Ohms. I think 3mils is not practical, is it?!
Maybe you should consult an application note (layout guidelines) from the RAM chip's manufacturer as with your trace width, 50 Ohms isn't an option.
You may hope that the termination in the RAM chip can be changed or you have to increase the trace width in combination with unequal layer thickness.
Wouldn't be an unusual prepreg thickness for a 10 - 12 layer PCB. But as I said, it's not suitable with 4-layer.
You didn't tell about the involved RAM controller or clock speed.
We are using the memory controller integrated to the Spartan 6 FPGA:
http://www.xilinx.com/support/docume...ides/ug388.pdf
I actually get the mentioned constraints from page 40 in the user guide specified in the above link.
The clock speed of the used Micron DDR3 is 1066MT/s DDR which means 533MHz effective clock.
They mention traces on inner layers only. When they assume between ground planes, Zo drops significantly. In that case you need the stripline model, not the microstrip.
They mention 165ps/inch, that is 1.54E8 m/s, that is an effective epsilon of 3.8. This doesn't match with ground under and below line, maybe they assume a burried microstrip (so with FR4 layer on top), that may have eff eps = 3.8.
They mention no Z0 here, so probably there are different flavours?
Hmmm, Does that mean that motherboard and graphics card PCB designers use strip lines when connecting the CPU/GPU to the DRAM ?! I can see traces clearly on some commercial PCBs like this: (see the traces between the GPU and the DDR3 memories)
http://www.techpowerup.com/reviews/H...ages/front.jpg
Are these microstrips or striplines?!
Can I use microstrips, and try to decrease the total thickness of the PCB from the typical 62mils value to another smaller value, say 20mils, so that if I'll use a 4-layer PCB, the thickness of each layer become (20/4) 5mils so I could achieve the ~50-Ohm Zo ?! or is the 62mil a must and we should increase the layers to decrease the thickness of each ?!
Added after 3 minutes:
P.S.
Another question, Does ODT (On-Die Termination) has anything to do with the impedance matching problem ?!
The (meandered/serpentine) lines are microstrips as the have a single ground. Can you determine the trace width and number of layers to get some impression if Zo.
Regarding the thinner total board thickness, this may be in conflict with mechanical requirements for mounting, PCB production and (mechanical) handling, so you should discuss this with client, user, etc.
As no other in the forum came with a solid answer to your questions, it requires you to study the documentation. If this still doesn’t give the answers it is time to contact the manufacturer. I know, when you buy small quantities, it can be difficult to get the right person.
Did you also try to determine the substrate thickness of the said boards? Surely it's at least 8, more likely 10 to 12 layers.
So they can achieve 50 ohm with their stackup.
Apart from 50 ohm impedance matching, I wonder how you'll achieve the necessary signal quality for 533 MHz RAM
clock on a four layer board. It's already difficult to provide sufficient supply bypassing and low impedance connection
for the different voltages.