RF Pad Trace Thickness
I am designing a RF PCB with a WiFi module. The trace thickness of the antenna feed is 4.9 mils for 50ohm impedance. This signal width is thin compared to the matching component pads (ie 0402 size) and edge SMA center diameter pads. Many of the layouts I've seen for RF boards define a stackup such that the 50ohm trace width is the same as component pad width.
Is it necessary to define a stackup so that the width is the same for the antenna trace and the SMD components? As long as I maintain 50ohm, would it matter what the trace thickness is compared to component pads?
Thanks
That is an unusal trace width for 50 Ohm. Have you double checked the calculation? What is your dielectric material thickness between microstrip trace and ground plane?
An SMD component itself will break the 50 Ohm line impedance, because the component itself has some impedance and is not a through connection. Sizing pads to fit the 50 Ohm line impedance is usually not possible and not required. I think what you have seen are designs where the layout connected pads with some non-50 ohm width that seemed reasonable. As long as total path length is small compared to the wavelength that's fine.
What we usually do at GHz frequencies, regardless of 50 Ohm line width, is to include the parasitic shunt capacitance to ground introduced by the pad (some fF).
Thickness from microstrip to ground plane is 3 mil. Trace thickness is 1.8 mil. Trace width is 4.9 mil. Dielectric constant is 4.
Using this calculator http://www.eeweb.com/toolbox/microstrip-impedance
It says the impedance is 51 Ohms. Am I missing something?
Why would some of the layouts compromise the match with a non-50ohm width to size it up to pad size?
If the dielectric thickness is indeed 3 mil, everything is fine. I was just surprised because in PCB we usually have much thicker dielectrics.
On usual PCB, width for 50 Ohm is much larger than yours. Then we would have difficulty to route between SMD with 50 Ohm lines, and the question is if that makes any sense anyway. The concept of controlled line impedance applies to blocks that have 50 Ohm input and output impedance, and the individual SMD are obviously no such 50 Ohm blocks. That is where layouters use some meaningful trace width that enables a dense layout with minimum path length, even if it's not 50 Ohm.
With 3 mils (0.075 μm) substrate thickness, even the smallest SMD components (e.g. 0201 size) implement a considerable parasitic capacitance in a 50 ohm system. As you say that it's a matching network, there should be no problem to correct the parasitics in the network calculation.