[Moved]: Verilog A code for Timer

时间：03-25 整理：3721RD 点击：

Hello,

I am trying to write verilog-A code to model a circuit that acts as an analog timer.
By default, the output is High, when it receives start signal (positive edge), the output should be low for a constant time (say 10u seconds) then it goes HIGH again.

Here is the code, however it doesn't seem to work.
Any help?

Code:

// VerilogA for ELC612, Analog_Timer, veriloga

`include "constants.vams"
`include "disciplines.vams"

module Analog_Timer(start,Vout);

input start;
output Vout;
electrical start, Vout;

parameter real ton=1u;
parameter real Vmax=1.5;
parameter real vtrans_clk=1.65;
parameter real vlogic_high=3.3;
parameter real vlogic_low = 0;
parameter trise=200e-9;
parameter tfall=200e-9;
parameter real tdel = 0;
integer next,temp;

analog begin

@ (cross( V(start) - vtrans_clk, +1,1n )) beginnext = Sabstime ;temp= 	0;
end	

@ (timer(next)) temp= 1;


V(Vout) <+ transition( temp? vlogic_high: vlogic_low,			   tdel, trise, tfall );


end
endmodule

Code:

// VerilogA for ELC612, Analog_Timer, veriloga

`include "constants.vams"
`include "disciplines.vams"

module Analog_Timer(start,Vout);

input start;
output Vout;
electrical start, Vout;

parameter real ton=10u;
parameter real Vmax=1.5;
parameter real vtrans_clk=1.65;
parameter real vlogic_high=3.3;
parameter real vlogic_low = 0;
parameter trise=200e-9;
parameter tfall=200e-9;
parameter real tdel = 0;

integer temp;
real next;

analog begin
   @(initial_step) begin
      temp = 1;
      next = Sabstime;
   end //initial_step

   @(timer(next)) temp= 1;

   @( cross(V(start)-vtrans_clk, +1, 1n) ) begin
      temp = 0;
      next = Sabstime + ton;
   end //cross

   V(Vout) <+ transition( temp ? vlogic_high:vlogic_low,
                                    tdel, trise, tfall );

end //analog
endmodule

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