NC是不是不支持参数化的class？
时间：10-02
整理：3721RD
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RT
报错提示：expecting an equal sign ('=') [SystemVerilog - 6.3.3]
classa_test_base #(type a_env) extends uvm_test;
...
endclass
Syntactically this identifier appears to begin a datatype but it does not refer to a visible datatype in the current scope.
`uvm_component_utils(a_tets_base#(a_env))
报错提示：expecting an equal sign ('=') [SystemVerilog - 6.3.3]
classa_test_base #(type a_env) extends uvm_test;
...
endclass
Syntactically this identifier appears to begin a datatype but it does not refer to a visible datatype in the current scope.
`uvm_component_utils(a_tets_base#(a_env))
#(type T =a_env)
额 见过这种写法 回头可以试一下 但是vcs的直接编译运行都是没问题的。