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How to solve "Dumping VCS Annotated Stack" error?

时间:10-02 整理:3721RD 点击:
There is a simple verilog file:
module test;
initial begin
$display("\nHello, World!\n");
end
endmodule

when I run the vcs :vcs -full64+v2k -sverilog test.v -o simv -R

But after compilation, There is a stack error:
Dumping VCS Annotated Stack:
#00x00000031718ac8fd in waitpid () from /lib64/libc.so.6
#10x000000317183e909 in do_system () from /lib64/libc.so.6
#20x000000317183ec40 in system () from /lib64/libc.so.6
#30x00007f4541f2a515 in SNPSle_10ee25eff68cd8461c9146fa1d0b35e87067f3c8015b313e639d2928478c79b3f673f99203bcf8be64600612100082236bffb2007f1e0ef9 () from /home/Tools/vcs/amd64/lib/liberrorinf.so
#40x00007f4541f2bc52 in SNPSle_10ee25eff68cd8461c9146fa1d0b35e87067f3c8015b313efba706aab251478fa49e66610e453774633a6c152e7ef778f2202cda681f3d4e () from /home/Tools/vcs/amd64/lib/liberrorinf.so
#50x00007f4541f23b0d in SNPSle_d35ca1ff70d465c2b9b1a72eee90a506fdd009d3de3db1de () from /home/Tools/vcs/amd64/lib/liberrorinf.so
... ... ...
No context available
Note: Execution of simv exited with code 1
CPU time: .152 seconds to compile + .216 seconds to elab + .216 seconds to link + .580 seconds in simulation

The OS is RHEL 6.5, VCS is v201412sp1
Some nice guys, could you tell me how can I solve this problem?

同问。

解决了, 是license问题

你是怎么解决的啊?

同问,小编怎么解决的

http://bbs.eetop.cn/viewthread.php?tid=553702&extra=&page=1
用这个license生成器可以,注意不要瞎鸡巴乱改notice,我就是因为乱改了一发出了这个错

我这里是偶尔会出错,应该不是license的问题吧,比如跑10个case,可能有一个出错

小编这个问题解决了吗?

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