vcs 的一个bug

在跑仿真的时候，当从一个RAM中读取数据时，发现数据不对。
仔细检查了写入的数据和地址，没错。
但是读出相应地址的数据时，会出错，数据不符合写入的值。
后来在always block里的读操作后面加了一个display的语句，结果读出的数据就对了。
这是否跟vcs仿真算法有关?
怀疑这是vcs的一个bug，不知是否如此。
可有哪位大牛出来指点指点?介绍个vcs相关的文档看看，理解理解vcs仿真的process。多谢多谢

It isn't very surpirise that you found only A vcs bug. I foundA LOT and reported them to synopsys support centrum.
However, They fixed bugs quite quickly and vcs is the best simulator for systemverilog I've used.

i m rookie,bugs visit rookie not much...
so, bugs' lover,
have you ever encountered the problem that i mentioned?

same with you. you should email vcs support.He'll give your an answer.

which version did you used?

侃侃什么bug

反映上去，

厉害！

牛xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx

9# whxqq
bug是多，不过软件做的还是很好的 忍了