system verilog keyword 'class' is not expected to be used in this context

这是本人在编写简单的验证平台时遇到的一个问题，看了case1.sv也没看出什么问题，请各位大神指教
编译错误如下：
Error-[SE] Syntax error
Following verilog source has syntax error :
"case1.sv", 4: token is 'class'
class case1 extends uvm_test;
^
System verilogkeyword 'class' is not expected to be used in this context.
1 warning
1 error
CPU time: .694 seconds to compile
case1.sv内容如下：
`ifndef CASE1_SV
`define CASE1_SV
class case1 extends uvm_test;
data_config data_cfg;
img_set_config img_set_cfg;
`uvm_component_utils(case1)
mod_adp_driver mod_adp_drv;
mod_adp_sequencer mod_adp_sqr;
function new(string name = "case1", uvm_component parent = null);
super.new(name, parent);
endfunction
virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
mod_adp_drv = mod_adp_driver::type_id::create("mod_adp_drv", this);
mod_adp_sqr = mod_adp_sequencer::type_id::create("mod_adp_sqr", this);
data_cfg = data_config::type_id::create("data_cfg", this);
data_cfg.build();
uvm_config_db#(data_config)::set(this, "mod_adp_sqr.*", "data_cfg", data_cfg);
img_set_cfg = img_set_config::type_id::create("img_set_cfg", this);
img_set_cfg.build();
uvm_config_db#(img_set_config)::set(this, "mod_adp_drv", "img_set_cfg", img_set_cfg);
uvm_config_db#(uvm_object_wrapper)::set(this, "mod_adp_sqr.main_phase.*", "default_sequence", mod_adp_sequence::type_id::get());
endfunction
virtual function viod connect_phase(uvm_phase phase);
super.connect_phase(phase);
mod_adp_drv.seq_item_port.connect(mod_adp_sqr.seq_item_export);
endfunction
endclass
`endif

请问你这个问题解决了吗?我也遇到了同样的问题

解决了，不过时间太久了，记不清了，应该是代码问题，最好仔细检查一下在该报错的文件之前编译的那个文件

好的，谢谢哈，遇到这个问题一直找不出来具体错在哪

我也遇到过，也记不清了。好像是我在windows下编辑的时候把文本格式搞错成utf-8了，后来用nedit打开，可以看到前面有个特殊字符。

你好，我也遇到这个问题了，请问你是如何解决的?

来自：https://verificationacademy.com/ ... s-declaration-issue
Usually a problem like this is because of an unfinished declaration that comes before it.
It would be much easier to find these kinds of problems if you did not `include everything in to one big file and could separately compile things. Our recommendation is to put each class in a separate file, and `include each class a package. Then you can compile each package independently. See an example of this here: http://verificationacademy.com/u ... rificationComponent

Thanks for your kindly reply.