关于register model的后门读写问题

我在register model中设置好后门路径，比如：top.reg_vif，然后我在top module中例化了reg_if为reg_vif。在top module中具体为：reg_if reg_vif(
.reg_tmrcsr({timer.timer_register.timer_irqen,
timer.timer_register.timer_pinsel,
timer.timer_register.timer_polarity,
timer.timer_register.timer_freerun,
timer.timer_register.timer_mode,
timer.timer_register.timer_enable}),
.reg_tmrpsr({timer.timer_register.timer_prescale,
timer.timer_register.timer_bypass,
timer.timer_register.timer_clksel}),

.reg_tmrcmr(timer.timer_register.timer_compare),
.reg_tmrcnr(timer.timer_register.timer_counter_reg));
然后后门写的时候，就只能写到reg_vif上，但是具体IP中的寄存器的值没变，咋回事?

不要沉啊