VCS中仿真带RAM IP的设计时出现的问题

本人在编写一个testbench时，遇到了一个问题，DUT中的RAM例化自ISE的IP，编译时在命令行加入了如下选项指向ISE提供的Lib

1. COMP_OPTS += -y /home/project_xu/ISE_lib/src/unisims
   
2. COMP_OPTS += -y /home/project_xu/ISE_lib/src/XilinxCoreLib
   
3. COMP_OPTS += -y /home/project_xu/ISE_lib/src/unimacro
   
4. COMP_OPTS += -y /home/project_xu/ISE_lib/src/simprims
   
5. COMP_OPTS += -y /home/project_xu/ISE_lib/src/uni9000
   
6. COMP_OPTS += +incdir+/home/project_xu/ISE_lib/src
   
7. COMP_OPTS += +libext+.v

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结果编译通过，但是在运行仿真时，终端始终显示如下，没有往下执行testbench，也没有报错：

1. Chronologic VCS simulator copyright 1991-2013
   
2. Contains Synopsys proprietary information.
   
3. Compiler version H-2013.06_Full64; Runtime version H-2013.06_Full64;Jan9 08:41 2015
   
4. ----------------------------------------------------------------
   
5. UVM-1.1d.VCS
   
6. (C) 2007-2013 Mentor Graphics Corporation
   
7. (C) 2007-2013 Cadence Design Systems, Inc.
   
8. (C) 2006-2013 Synopsys, Inc.
   
9. (C) 2011-2013 Cypress Semiconductor Corp.
   
10. ----------------------------------------------------------------
    
11. 
    
12. ***********IMPORTANT RELEASE NOTES************
    
13. 
    
14. You are using a version of the UVM library that has been compiled
    
15. with `UVM_NO_DEPRECATED undefined.
    
16. See http://www.eda.org/svdb/view.php?id=3313 for more details.
    
17. 
    
18. You are using a version of the UVM library that has been compiled
    
19. with `UVM_OBJECT_MUST_HAVE_CONSTRUCTOR undefined.
    
20. See http://www.eda.org/svdb/view.php?id=3770 for more details.
    
21. 
    
22. (Specify +UVM_NO_RELNOTES to turn off this notice)
    
23. 
    
24. Block Memory Generator CORE Generator module TOP.U_CFAI.u_line_buf0.inst.native_mem_module.blk_mem_gen_v7_3_inst is using a behavioral model for simulation which will not precisely model memory collision behavior.
    
25. Block Memory Generator CORE Generator module TOP.U_CFAI.u_line_buf1.inst.native_mem_module.blk_mem_gen_v7_3_inst is using a behavioral model for simulation which will not precisely model memory collision behavior.
    
26. Block Memory Generator CORE Generator module TOP.U_CFAI.u_line_buf2.inst.native_mem_module.blk_mem_gen_v7_3_inst is using a behavioral model for simulation which will not precisely model memory collision behavior.
    
27. Block Memory Generator CORE Generator module TOP.U_CFAI.u_line_buf3.inst.native_mem_module.blk_mem_gen_v7_3_inst is using a behavioral model for simulation which will not precisely model memory collision behavior.

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然后尝试了带乘法器IP的DUT，仿真没有问题，在网上看到有人说ISE自带的IP生成的Block Ram是不能被VCS编译的，请问各位这可能是哪里出问题了?急~急~急~

LZ这个问题解决了么?我也碰到了。