uvm1.1 使用VCS验证，如何设置

求助：
各位前辈，大侠，我是个UVM初学，最近在这里下了个UVM1.1的LAB，想用来学习UVM，但是把文件解压之后在.cshrc下设置了环境变量指向其bin目录。
但是后面有安装覆盖文件和编译就不知道应该怎么按照VCS版本配置了，我用的VCS是 VCS-MX E-2011.03-SP1
希望能有前辈出来指点下，不胜感激！

自己顶下，真的很急

很简单吧，按照readme，把软件配置好，就可以跑了吧。

readme 我也看了就是下面这个不太懂的，谢谢能具体指点下么
You must then obtain from your SystemVerilog tool vendor a tool-specific
distribution overlay. That overlay may be specific to the machine
architecture and/or operating system you are using. Make sure you provide
the output of the '$UVM_HOME/bin/uvm_os_name' script as well as the version
of the simulator you are using when requesting a UVM overlay from your vendor.
% $UVM_HOME/bin/uvm_os_name
IUS:% irun -version
Questa:% vlog -version
VCS:% vcs -ID
Follow the installation instructions provided by your tool vendor for
installing the overlay in your UVM installation.
Note to EDA vendors: to support multiple tool-specific overlays in the
same UVM distribution, please locate any tool-specific files in a
tool-specific sub-directory.

readme 我也看了，请宁能具体指点下怎么配置么，十分感谢！

这个是看你eda工具能支持的uvm自带的版本，当然你可以自己编译新的uvm。看工具手册吧，ius简单点，直接irun -uvm ....