icc itf 转 tluplus 问题 求助？
时间：10-02
整理：3721RD
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1. ICC tluplus文件 问题
ICC所用到的tluplus文件，由itf文件转换得到tluplus，（ grdgenxo -itf2TLUPlus -i -o ），然后在运行ICC时遇到下面的问题：
TLU+ based extraction:
Resistance based on max model.
Using operating temperature of25.00 degrees.
EKL: layer poly has pitchInfo: raw tluplus is detected
Info: raw tluplus is detected
This following CapTable is missing when accessing:
TLUPlus File = "/home/GSMC_A018S6D0_TRAN_MIN.tluplus"; Reference Layer = "metal1"; Bottom Layer = "Substrate"; Top Layer = "metal2"; Table Type = "Lateral"
EKL_VALUE: error, "/0."
EKL_VALUE: error, "/0."
EKL_VALUE: error, "/0."
This following CapTable is missing when accessing:
TLUPlus File = "/home/GSMC_A018S6D0_TRAN_MIN.tluplus"; Reference Layer = "metal2"; Bottom Layer = "Substrate"; Top Layer = "metal3"; Table Type = "Lateral"
EKL_VALUE: error, "/0."
EKL_VALUE: error, "/0."
EKL_VALUE: error, "/0."
This following CapTable is missing when accessing:
TLUPlus File = "/home/GSMC_A018S6D0_TRAN_MIN.tluplus"; Reference Layer = "metal3"; Bottom Layer = "Substrate"; Top Layer = "metal4"; Table Type = "Lateral"
EKL_VALUE: error, "/0."
EKL_VALUE: error, "/0."
EKL_VALUE: error, "/0."
This following CapTable is missing when accessing:
TLUPlus File = "/home/GSMC_A018S6D0_TRAN_MIN.tluplus"; Reference Layer = "metal4"; Bottom Layer = "Substrate"; Top Layer = "metal5"; Table Type = "Lateral"
EKL_VALUE: error, "/0."
EKL_VALUE: error, "/0."
This following CapTable is missing when accessing:
TLUPlus File = "/home/GSMC_A018S6D0_TRAN_MIN.tluplus"; Reference Layer = "metal5"; Bottom Layer = "Substrate"; Top Layer = "metal6"; Table Type = "Lateral"
Getting the info of via resistance from TLU+ model
can not find resistance in tluplus for polyCont; skip ...
can not find resistance in tluplus for polyCont; skip ...
lower mask id 0, upper mask id 1, via layer 25, resistivity 0.000000
can not find resistance in tluplus for via1; skip ...
can not find resistance in tluplus for via1; skip ...
lower mask id 1, upper mask id 2, via layer 41, resistivity 0.000000
can not find resistance in tluplus for via2; skip ...
can not find resistance in tluplus for via2; skip ...
lower mask id 2, upper mask id 3, via layer 42, resistivity 0.000000
can not find resistance in tluplus for via3; skip ...
lower mask id 3, upper mask id 4, via layer 43, resistivity 0.000000
lower mask id 4, upper mask id 5, via layer 44, resistivity 0.000000
lower mask id 5, upper mask id 6, via layer 45, resistivity 0.000000
EKL: max metal layer: 6
Ignoring all CONN views
Warning: No power/ground pads are specified and no virtual pads are defined. (PNA-138)
Geometry mapping took0.18 seconds
Name of design : Decimator_Top
Number of cell instance masters in the library : 92
Number of cell instances in the design : 16741
Power Network Synthesis Begins ...
Target IR drop : 180.000 mV
Processing net VDD ...
Average power dissipation in Decimator_Top :20.00 mW
Power supply voltage :1.80 V
Average current in Decimator_Top :11.11 mA
terminate called after throwing an instance of 'TLUPlus_In_Mem_Exception_struct'
The tool has just encountered a fatal error:
If you encountered this fatal error when using the most recent
Synopsys release, submit this stack trace and a test case that
reproduces the problem to the Synopsys Support Center by using
Enter A Call at http://solvnet.synopsys.com/EnterACall.
* For information about the latest software releases, go to the Synopsys
SolvNet Release Library at http://solvnet.synopsys.com/ReleaseLibrary.
* For information about required Operating System patches, go to
http://www.synopsys.com/support
Fatal: Internal system error, cannot recover.
Error code=6
Release = 'C-2009.06-ICC-SP5'Architecture = 'linux'Program = 'icc_shell'
Exec = '/eda/Synopsys/icc/linux/syn/bin/galaxy_icc_exec'
'278572716 278572984 -6912 7833345 290688710 290678825 290678867 290679094 228494007 228497135 228366567 228366753 228063053 228244610 227986373 249736335 248884359 249508678 249244061 249334572 249477428 249479696 249328761 249383954 248749722 248751476 215764014 168206246 164783345 262062351 280690266 280696346 280697184 262029968 262042529 262062351 280690266 280696346 280855410 280876789 280700375 280902385 262054765 157764789 157747021 158476664 158436813 158443326 158422687 158225703 157441729 157431523 134624015 161026677 134622827 134623808 7749276'
应该怎样解决?求大神指导~
--------------------------------------------------------------------------------------------------------------------------------------------------------
2. tlup_map 问题
上面的tluplus问题是否是由tlup_map造成呢?foundry提供了两个．map文件，一个是GSMC_GDSII_Layer_Mapping_Table_for_Virtuoso.map，一个是GDS2Layer.map(文件附后)。于是当时tlup_map设置如下
set tlup_map "gdsLayers.map"
看论坛里面有童子说map文件可以自己写，具体怎样写呢?
附１：GDS2Layer．map文件
;Avanti！Layer GDS2Layer[:GDS2DataType]
66; Diffusion
11; N-Well
1212; Poly
1515; P+
1414; N+
5353; VTH
2525; Contact
3131; Metal1
131 131 ; Metal1 text
4141; Mvia1
3232; Metal2
132 132 ; Metal2 text
5050; Cut
4242; Mvia2
3333; Metal3
133 133 ; Metal3 text
4343; Mvia3
3434; Metal4
134 134 ; Metal4 text
4444; Mvia4
3535; Metal5
135 135 ; Metal5 text
4545; Mvia5
3636; Metal6
136 136 ; Metal6 text
6060; prBoundary
2727; Passivation
2020; ESD1
1919; PLH
1818; NLH
1717; PLL
1616; NLL
99; DG
2121; SAB
;9696; Rea_P1
218 168:1 ;m1b
219 168:2 ;m2b
220 168:3 ;m3b
216 168:4 ;m4b
239 168:5 ;m5b
240 168:6 ;m6b
224 168:11 ;v1b
225 168:12 ;v2b
217 168:13 ;v3b
241 168:14 ;v4b
242 168:15 ;v5b
243 168:16 ;v6b
附2：GSMC_GDSII_Layer_Mapping_Table_for_Virtuoso.map 文件
# $Id: GSMC_GDSII_Layer_Mapping_Table_for_Virtuoso.map,v 1.0 2011/04/14 03:20:21 lym Exp $
# Reference Document: GDSII_Layer_Mapping_Table_for_Customer_V0.30 doc
# $Log: GSMC_GDSII_Layer_Mapping_Table_for_Virtuoso.map,v $
# Revision 1.02011/04/14 03:20:21lym
# New creation
# Add VTH/BCI layer based on GSMC_A013S7G0_Virtuoso_500.map_V1.6
#
###########################################################################
NWdrawing10#NWELL
NWtext195#Text of NWELL
PWdrawing20#PWELL
PWtext295#Text of PWELL
PWBLKdrawing30#PWELL Block Layer
DNWdrawing40#Deep NWELL
VSTIdrawing50#Very Shallow Trench
VSTIildtnh541#ILD Trench
ACTdrawing60#Active area
ACTdummy610#Dummy Act(for customer)
LVNWdrawing70#Low voltage NW
LVPWdrawing80#Low voltage PW
TGOdrawing90#Thick oxide 1
TGO2drawing100#Thick oxide 2
GATEdrawing120#Poly gate
GATEdummy1210#Dummy Gate(for customer)
GATEtext1295#Poly gate text layer
NPLUSdrawing140#Nimp
PPLUSdrawing150#Pimp
NLDD1drawing160#NLDD implant for Device 1
PLDD1drawing170#PLDD implant for Device 1
NLDD2drawing180#NLDD implant for Device 2
PLDD2drawing190#PLDD implant for Device 2
ESDdrawing200#ESD implant
SABdrawing210#Non silicided area definition
VTNdrawing220#NMOS VT implant
VTPdrawing230#PMOS VT implant
CTdrawing250#Contact
PLYMDdrawing260#Polymide for passivation
PAdrawing270#Passivation
PArdumm1271#Passivation(Negative Resistor)
OPCdrawing280#OPC block layer
OPCrdumm1281#OPC block layer for ACT
OPCrdumm2282#OPC block layer for GATE
OPCrdumm3283#OPC block layer for M1
EXCLdrawing290#Dummy layer for DRC unchecked
FUSEdrawing300#FUSE
M1drawing310#Metal1
M1dummy3110#Dummy Metal1(for customer)
M2drawing320#Metal2
M2dummy3210#Dummy Metal2(for customer)
M3drawing330#Metal3
M3dummy3310#Dummy Metal3(for customer)
M4drawing340#Metal4
M4dummy3410#Dummy Metal4(for customer)
M5drawing350#Metal5
M5dummy3510#Dummy Metal5(for customer)
M6drawing360#Metal6
M6dummy3610#Dummy Metal6(for customer)
M7drawing370#Metal7
M7dummy3710#Dummy Metal7(for customer)
M8drawing380#Metal8
M8dummy3810#Dummy Metal8(for customer)
M9drawing390#Metal9
M9dummy3910#Dummy Metal9(for customer)
LIdrawing400#Local Interconnection Line
MV1drawing410#Via1
MV2drawing420#Via2
MV3drawing430#Via3
MV4drawing440#Via4
MV5drawing450#Via5
MV6drawing460#Via6
MV7drawing470#Via7
MV8drawing480#Via8
NACDdrawing490#Dummy ACT exclusion
PSUB2drawing500#Psub2 for multipower isolation
DUM_MCTdrawing520#MIM Capacitor dummy Layer for MIM identified
VTHdrawing530#For ULL eflash core devices
VTCdrawing540#Cell VT implant
ACTRdrawing590#For STI plannarization
prBoundarydrawing600#prBoundary
NFLDdrawing610#N-field implant
DUM_DIOdrawing620#Diode dummy layer for LVS
DUM_BJTdrawing630#BJT dummy layer for LVS
DUM_BJTiptag6363#IP description layer,it couldn't be modified to lose correct IP info
NGRDdrawing640#N-grade implant
PGRDdrawing650#P-grade implant
DUM_CAPdrawing660#POLY capacitor dummy layer for LVS
NWDMYdrawing670#NWELL resistor dummy layer for DRC and LVS
RNDMYdrawing680#N+ Poly resistor dummy layer for LVS
RNDMYrdumm1681#NLDD implant blocking
RPDMYdrawing700#P+ Poly resistor dummy layer for LVS
RPDMYrdumm1701#PLDD implant blocking
DUM_RMdrawing710#Poly resistor dummy for LVS
DUM_RMrdumm1711#Metal1 resistor dummy for LVS
DUM_RMrdumm2712#Metal2 resistor dummy for LVS
DUM_RMrdumm3713#Metal3 resistor dummy for LVS
DUM_RMrdumm4714#Metal4 resistor dummy for LVS
DUM_RMrdumm5715#Metal5 resistor dummy for LVS
DUM_RMrdumm6716#Metal6 resistor dummy for LVS
DUM_RMrdumm7717#Metal7 resistor dummy for LVS
DUM_RMrdumm307130#Thin Film metal resistor marking layer for lvs
DUM_RMrt3_lvs7120#3 terminal cap,res identified layer for lvs
DUM_RMrt4_lvs7121#4 terminal cap,res identified layer for lvs
DUM_CMdrawing720#Parasitic Metal capacitor dummy layer
L_IN_1Mdrawing730#Non dummy area of Metal1
L_IN_2Mdrawing740#Non dummy area of Metal2
L_IN_3Mdrawing750#Non dummy area of Metal3
L_IN_4Mdrawing760#Non dummy area of Metal4
L_IN_5Mdrawing770#Non dummy area of Metal5
L_IN_6Mdrawing780#Non dummy area of Metal6
RING_MCTdrawing790#For dummy MIM capacitor ring use
MTTdrawing800#For Thick Top metal as an inductor
CGOdrawing820#Pad out layer for staggered IO
IORLdrawing830#IO rule marking layer
CSRCdrawing840#IO special
BNdrawing860#Buried NPLUS
BTC_PECTdrawing880#Butting Contact/PNP Emitter Contact
CISOdrawing890#Cell isolation (for ROM process)
VTNDdrawing900#Vt implant for N-ch depletion layer
VTPDdrawing910#Vt implant for P-ch depletion layer
DUM_RODdrawing920#Active resistor dummy layer for LVS
N1GDdrawing930#Non dummy area for gate
L_IN_7Mdrawing940#Non dummy area of Metal7
L_IN_8Mdrawing950#Non dummy area of Metal8
VTNLdrawing960#Vt implant layer for NMOS lower threhold voltage
VTPLdrawing970#Vt implant layer for PMOS lower threhold voltage
VTNHdrawing980#Vt implant layer for NMOS higher threhold voltage
VTPHdrawing990#Vt implant layer for PMOS higher threhold voltage
Boundarydrawing1000#Chip Boundary Layer
ROMCdrawing1010#ROM code implant
PFLDdrawing1020#P-field implant
INDDMYdrawing1030#Dummy layer for metal inductor
MDBLKdrawing1040#Dummy GATE and Metal Blocking layer
HVNWdrawing1050#NWELL for high voltage NMOS
HVPWdrawing1060#NWELL for high voltage PMOS
MCTdrawing1070#Metal Capacitor Top Layer
FLGTdrawing1080#Floating gate definition
FLGT2drawing1090#Floating gate 2definition
PLUGdrawing1100#Code dummy in MROM
FGCTdrawing1110#Connect point with floating gate
WLSP_SPACERdrawing1140#Word line space
MPOLdrawing1150#Memory poly
GSTIdrawing1160#Additional STI etching
ZNIPdrawing1170#Zener implant
HALIdrawing1180#Special drawing layer,for LDD implant into anti-well region
HRdrawing1190#High resistance resistor
HVPO_HVGOdrawing1200#High Voltage Poly
VTMNdrawing1220#2nd Medium VTN implant
VTMPdrawing1230#2nd Medium VTP implant
PESDdrawing1240#PESD implant
INAG2drawing1250#Active and poly ignore layer for LVS
BPIdrawing1260#PIP capacitor bottom plate implant
PCTdrawing1270#Poly capacitor top plate
NPIdrawing1280#N-type poly gate implant
INAGdrawing1300#Active and poly ignore layer for LVS
M1_TEXTdrawing1310#Metal1 text layer
M1_TEXTrdumm11311#Text layer
M2_TEXTdrawing1320#Metal2 text layer
M3_TEXTdrawing1330#Metal3 text layer
M4_TEXTdrawing1340#Metal4 text layer
M5_TEXTdrawing1350#Metal5 text layer
M6_TEXTdrawing1360#Metal6 text layer
M7_TEXTdrawing1370#Metal7 text layer
M8_TEXTdrawing1380#Metal8 text layer
M9_TEXTdrawing1390#Metal9 text layer
MVNWdrawing1410#Medium Voltage Nwell
MVPWdrawing1420#Medium Voltage Pwell
PMDMYdrawing1530#Identify Metal Fuse PMDMY
NLDD0drawing1560#NLDD implant for 1.8v device in Embeded Flash
MCEL_CELLdrawing1580#Memory Cell
PLDD0drawing1600#PLDD implant for 1.8v device in Embeded Flash
IPBoundarydrawing1610#For Flash IP
IPBoundaryrdumm11611#Customized IP boundary 1
IPBoundaryrdumm21612#Customized IP boundary 2
IPBoundarydummy16110#Photonics IP boundary
IPBoundarytext16195#IP_TEXT,CELL_TEXT
DUM_RFdrawing1620#RF device marking layer
DUM_RFdumrfd16211#Identify RF mod drain terminal
DUM_RFdumrfs16212#Extract metal space parameter of inductor for lvs
DUM_RFdumrfw16213#Extract metal width parameter of inductor for lvs
DUM_RFdumrfr16214#Extract inner diameter param of inductor for lvs
DUM_RFdumrfsym 16215#Symmetrical inductor marking layer
DUM_RFdumrfstd 16216#Standard inductor marking layer
DUM_RFlabass16231#Label layer for assura lvs
DUM_RFlabcal116232#Label layer 1 for calibre lvs
DUM_RFlabcal216233#Label layer 2 for calibre lvs
DUM_RFlabcal316234#Label layer 3 for calibre lvs
DUM_RFlabcal416235#Label layer 4 for calibre lvs
DUM_RFlabcal516236#Label layer 5 for calibre lvs
DUM_RFlabcal616237#Label layer 6 for calibre lvs
DUM_RFlabcal716238#Label layer 7 for calibre lvs
DUM_RFlabcal816239#Label layer 8 for calibre lvs
DUM_RFxrcblk16240#Dummy layer for calibre xrc extraction
DUM_VARdrawing1630#Varactor device marking layer
UDEFdrawing1680#special specified layer by customer
HVdrawing1700#HV region for 32V device
HVhv2417024#Marking layer for 24V device
IHVPWdrawing1710#Isolated HVPW
HDNWdrawing1720#High voltage DNW
MCB_MCT2drawing1730#Metal Capacitor Bottom layer
LMARKdrawing1740#for laster repairing machine alignment
CVTNdrawing1750#Cell VT impant for NMOS
CVTPdrawing1760#Cell VT impant for PMOS
LVIDdrawing1770#For lowpower device Vt implant
NWDEdrawing1780#NW Drain Extension Implant
PWDEdrawing1790#PW Drain Extension Implant
ESDT1drawing1800#ESD covering layer for Power Pin
ESDT2drawing1810#ESD covering layer for 5V tolerant
EPOLYdrawing1820#Emitter Poly
BPOLYdrawing1830#Base Poly
NPNEWdrawing1840#NPN Emitter window
NPNSCIdrawing1850#NPN Selective collector implant
NPNCOLLdrawing1860#NPN Collector implant
NPNdrawing1870#NPN open
ZNVTdrawing1880#Blockage of zero implant
CGCTdrawing1890#Control Gate Contact
BCIdrawing1900#Body Contact Implant
## As the layer-number of these layers beyond the scope of user-definable in virtuoso_5141,
## So you will not see these layers definition in .tf file.
ACT_DUMdrawing2060#dummy ACT layer
SDLdrawing2110#Special Device layer(for HV process)
GATE_DUMdrawing2120#dummy GATE layer
M1_DUMdrawing2310#dummy M1
M2_DUMdrawing2320#dummy M2
M3_DUMdrawing2330#dummy M3
M4_DUMdrawing2340#dummy M4
M5_DUMdrawing2350#dummy M5
M6_DUMdrawing2360#dummy M6
M7_DUMdrawing2370#dummy M7
M8_DUMdrawing2380#dummy M8
M9_DUMdrawing2390#dummy M9
SCHCTdrawing2410#Schottky Contact
ICC所用到的tluplus文件，由itf文件转换得到tluplus，（ grdgenxo -itf2TLUPlus -i
TLU+ based extraction:
Resistance based on max model.
Using operating temperature of25.00 degrees.
EKL: layer poly has pitch
Info: raw tluplus is detected
This following CapTable is missing when accessing:
TLUPlus File = "/home/GSMC_A018S6D0_TRAN_MIN.tluplus"; Reference Layer = "metal1"; Bottom Layer = "Substrate"; Top Layer = "metal2"; Table Type = "Lateral"
EKL_VALUE: error, "/0."
EKL_VALUE: error, "/0."
EKL_VALUE: error, "/0."
This following CapTable is missing when accessing:
TLUPlus File = "/home/GSMC_A018S6D0_TRAN_MIN.tluplus"; Reference Layer = "metal2"; Bottom Layer = "Substrate"; Top Layer = "metal3"; Table Type = "Lateral"
EKL_VALUE: error, "/0."
EKL_VALUE: error, "/0."
EKL_VALUE: error, "/0."
This following CapTable is missing when accessing:
TLUPlus File = "/home/GSMC_A018S6D0_TRAN_MIN.tluplus"; Reference Layer = "metal3"; Bottom Layer = "Substrate"; Top Layer = "metal4"; Table Type = "Lateral"
EKL_VALUE: error, "/0."
EKL_VALUE: error, "/0."
EKL_VALUE: error, "/0."
This following CapTable is missing when accessing:
TLUPlus File = "/home/GSMC_A018S6D0_TRAN_MIN.tluplus"; Reference Layer = "metal4"; Bottom Layer = "Substrate"; Top Layer = "metal5"; Table Type = "Lateral"
EKL_VALUE: error, "/0."
EKL_VALUE: error, "/0."
This following CapTable is missing when accessing:
TLUPlus File = "/home/GSMC_A018S6D0_TRAN_MIN.tluplus"; Reference Layer = "metal5"; Bottom Layer = "Substrate"; Top Layer = "metal6"; Table Type = "Lateral"
Getting the info of via resistance from TLU+ model
can not find resistance in tluplus for polyCont; skip ...
can not find resistance in tluplus for polyCont; skip ...
lower mask id 0, upper mask id 1, via layer 25, resistivity 0.000000
can not find resistance in tluplus for via1; skip ...
can not find resistance in tluplus for via1; skip ...
lower mask id 1, upper mask id 2, via layer 41, resistivity 0.000000
can not find resistance in tluplus for via2; skip ...
can not find resistance in tluplus for via2; skip ...
lower mask id 2, upper mask id 3, via layer 42, resistivity 0.000000
can not find resistance in tluplus for via3; skip ...
lower mask id 3, upper mask id 4, via layer 43, resistivity 0.000000
lower mask id 4, upper mask id 5, via layer 44, resistivity 0.000000
lower mask id 5, upper mask id 6, via layer 45, resistivity 0.000000
EKL: max metal layer: 6
Ignoring all CONN views
Warning: No power/ground pads are specified and no virtual pads are defined. (PNA-138)
Geometry mapping took0.18 seconds
Name of design : Decimator_Top
Number of cell instance masters in the library : 92
Number of cell instances in the design : 16741
Power Network Synthesis Begins ...
Target IR drop : 180.000 mV
Processing net VDD ...
Average power dissipation in Decimator_Top :20.00 mW
Power supply voltage :1.80 V
Average current in Decimator_Top :11.11 mA
terminate called after throwing an instance of 'TLUPlus_In_Mem_Exception_struct'
The tool has just encountered a fatal error:
If you encountered this fatal error when using the most recent
Synopsys release, submit this stack trace and a test case that
reproduces the problem to the Synopsys Support Center by using
Enter A Call at http://solvnet.synopsys.com/EnterACall.
* For information about the latest software releases, go to the Synopsys
SolvNet Release Library at http://solvnet.synopsys.com/ReleaseLibrary.
* For information about required Operating System patches, go to
http://www.synopsys.com/support
Fatal: Internal system error, cannot recover.
Error code=6
Release = 'C-2009.06-ICC-SP5'Architecture = 'linux'Program = 'icc_shell'
Exec = '/eda/Synopsys/icc/linux/syn/bin/galaxy_icc_exec'
'278572716 278572984 -6912 7833345 290688710 290678825 290678867 290679094 228494007 228497135 228366567 228366753 228063053 228244610 227986373 249736335 248884359 249508678 249244061 249334572 249477428 249479696 249328761 249383954 248749722 248751476 215764014 168206246 164783345 262062351 280690266 280696346 280697184 262029968 262042529 262062351 280690266 280696346 280855410 280876789 280700375 280902385 262054765 157764789 157747021 158476664 158436813 158443326 158422687 158225703 157441729 157431523 134624015 161026677 134622827 134623808 7749276'
应该怎样解决?求大神指导~
--------------------------------------------------------------------------------------------------------------------------------------------------------
2. tlup_map 问题
上面的tluplus问题是否是由tlup_map造成呢?foundry提供了两个．map文件，一个是GSMC_GDSII_Layer_Mapping_Table_for_Virtuoso.map，一个是GDS2Layer.map(文件附后)。于是当时tlup_map设置如下
set tlup_map "gdsLayers.map"
看论坛里面有童子说map文件可以自己写，具体怎样写呢?
附１：GDS2Layer．map文件
;Avanti！Layer GDS2Layer[:GDS2DataType]
66; Diffusion
11; N-Well
1212; Poly
1515; P+
1414; N+
5353; VTH
2525; Contact
3131; Metal1
131 131 ; Metal1 text
4141; Mvia1
3232; Metal2
132 132 ; Metal2 text
5050; Cut
4242; Mvia2
3333; Metal3
133 133 ; Metal3 text
4343; Mvia3
3434; Metal4
134 134 ; Metal4 text
4444; Mvia4
3535; Metal5
135 135 ; Metal5 text
4545; Mvia5
3636; Metal6
136 136 ; Metal6 text
6060; prBoundary
2727; Passivation
2020; ESD1
1919; PLH
1818; NLH
1717; PLL
1616; NLL
99; DG
2121; SAB
;9696; Rea_P1
218 168:1 ;m1b
219 168:2 ;m2b
220 168:3 ;m3b
216 168:4 ;m4b
239 168:5 ;m5b
240 168:6 ;m6b
224 168:11 ;v1b
225 168:12 ;v2b
217 168:13 ;v3b
241 168:14 ;v4b
242 168:15 ;v5b
243 168:16 ;v6b
附2：GSMC_GDSII_Layer_Mapping_Table_for_Virtuoso.map 文件
# $Id: GSMC_GDSII_Layer_Mapping_Table_for_Virtuoso.map,v 1.0 2011/04/14 03:20:21 lym Exp $
# Reference Document: GDSII_Layer_Mapping_Table_for_Customer_V0.30 doc
# $Log: GSMC_GDSII_Layer_Mapping_Table_for_Virtuoso.map,v $
# Revision 1.02011/04/14 03:20:21lym
# New creation
# Add VTH/BCI layer based on GSMC_A013S7G0_Virtuoso_500.map_V1.6
#
###########################################################################
NWdrawing10#NWELL
NWtext195#Text of NWELL
PWdrawing20#PWELL
PWtext295#Text of PWELL
PWBLKdrawing30#PWELL Block Layer
DNWdrawing40#Deep NWELL
VSTIdrawing50#Very Shallow Trench
VSTIildtnh541#ILD Trench
ACTdrawing60#Active area
ACTdummy610#Dummy Act(for customer)
LVNWdrawing70#Low voltage NW
LVPWdrawing80#Low voltage PW
TGOdrawing90#Thick oxide 1
TGO2drawing100#Thick oxide 2
GATEdrawing120#Poly gate
GATEdummy1210#Dummy Gate(for customer)
GATEtext1295#Poly gate text layer
NPLUSdrawing140#Nimp
PPLUSdrawing150#Pimp
NLDD1drawing160#NLDD implant for Device 1
PLDD1drawing170#PLDD implant for Device 1
NLDD2drawing180#NLDD implant for Device 2
PLDD2drawing190#PLDD implant for Device 2
ESDdrawing200#ESD implant
SABdrawing210#Non silicided area definition
VTNdrawing220#NMOS VT implant
VTPdrawing230#PMOS VT implant
CTdrawing250#Contact
PLYMDdrawing260#Polymide for passivation
PAdrawing270#Passivation
PArdumm1271#Passivation(Negative Resistor)
OPCdrawing280#OPC block layer
OPCrdumm1281#OPC block layer for ACT
OPCrdumm2282#OPC block layer for GATE
OPCrdumm3283#OPC block layer for M1
EXCLdrawing290#Dummy layer for DRC unchecked
FUSEdrawing300#FUSE
M1drawing310#Metal1
M1dummy3110#Dummy Metal1(for customer)
M2drawing320#Metal2
M2dummy3210#Dummy Metal2(for customer)
M3drawing330#Metal3
M3dummy3310#Dummy Metal3(for customer)
M4drawing340#Metal4
M4dummy3410#Dummy Metal4(for customer)
M5drawing350#Metal5
M5dummy3510#Dummy Metal5(for customer)
M6drawing360#Metal6
M6dummy3610#Dummy Metal6(for customer)
M7drawing370#Metal7
M7dummy3710#Dummy Metal7(for customer)
M8drawing380#Metal8
M8dummy3810#Dummy Metal8(for customer)
M9drawing390#Metal9
M9dummy3910#Dummy Metal9(for customer)
LIdrawing400#Local Interconnection Line
MV1drawing410#Via1
MV2drawing420#Via2
MV3drawing430#Via3
MV4drawing440#Via4
MV5drawing450#Via5
MV6drawing460#Via6
MV7drawing470#Via7
MV8drawing480#Via8
NACDdrawing490#Dummy ACT exclusion
PSUB2drawing500#Psub2 for multipower isolation
DUM_MCTdrawing520#MIM Capacitor dummy Layer for MIM identified
VTHdrawing530#For ULL eflash core devices
VTCdrawing540#Cell VT implant
ACTRdrawing590#For STI plannarization
prBoundarydrawing600#prBoundary
NFLDdrawing610#N-field implant
DUM_DIOdrawing620#Diode dummy layer for LVS
DUM_BJTdrawing630#BJT dummy layer for LVS
DUM_BJTiptag6363#IP description layer,it couldn't be modified to lose correct IP info
NGRDdrawing640#N-grade implant
PGRDdrawing650#P-grade implant
DUM_CAPdrawing660#POLY capacitor dummy layer for LVS
NWDMYdrawing670#NWELL resistor dummy layer for DRC and LVS
RNDMYdrawing680#N+ Poly resistor dummy layer for LVS
RNDMYrdumm1681#NLDD implant blocking
RPDMYdrawing700#P+ Poly resistor dummy layer for LVS
RPDMYrdumm1701#PLDD implant blocking
DUM_RMdrawing710#Poly resistor dummy for LVS
DUM_RMrdumm1711#Metal1 resistor dummy for LVS
DUM_RMrdumm2712#Metal2 resistor dummy for LVS
DUM_RMrdumm3713#Metal3 resistor dummy for LVS
DUM_RMrdumm4714#Metal4 resistor dummy for LVS
DUM_RMrdumm5715#Metal5 resistor dummy for LVS
DUM_RMrdumm6716#Metal6 resistor dummy for LVS
DUM_RMrdumm7717#Metal7 resistor dummy for LVS
DUM_RMrdumm307130#Thin Film metal resistor marking layer for lvs
DUM_RMrt3_lvs7120#3 terminal cap,res identified layer for lvs
DUM_RMrt4_lvs7121#4 terminal cap,res identified layer for lvs
DUM_CMdrawing720#Parasitic Metal capacitor dummy layer
L_IN_1Mdrawing730#Non dummy area of Metal1
L_IN_2Mdrawing740#Non dummy area of Metal2
L_IN_3Mdrawing750#Non dummy area of Metal3
L_IN_4Mdrawing760#Non dummy area of Metal4
L_IN_5Mdrawing770#Non dummy area of Metal5
L_IN_6Mdrawing780#Non dummy area of Metal6
RING_MCTdrawing790#For dummy MIM capacitor ring use
MTTdrawing800#For Thick Top metal as an inductor
CGOdrawing820#Pad out layer for staggered IO
IORLdrawing830#IO rule marking layer
CSRCdrawing840#IO special
BNdrawing860#Buried NPLUS
BTC_PECTdrawing880#Butting Contact/PNP Emitter Contact
CISOdrawing890#Cell isolation (for ROM process)
VTNDdrawing900#Vt implant for N-ch depletion layer
VTPDdrawing910#Vt implant for P-ch depletion layer
DUM_RODdrawing920#Active resistor dummy layer for LVS
N1GDdrawing930#Non dummy area for gate
L_IN_7Mdrawing940#Non dummy area of Metal7
L_IN_8Mdrawing950#Non dummy area of Metal8
VTNLdrawing960#Vt implant layer for NMOS lower threhold voltage
VTPLdrawing970#Vt implant layer for PMOS lower threhold voltage
VTNHdrawing980#Vt implant layer for NMOS higher threhold voltage
VTPHdrawing990#Vt implant layer for PMOS higher threhold voltage
Boundarydrawing1000#Chip Boundary Layer
ROMCdrawing1010#ROM code implant
PFLDdrawing1020#P-field implant
INDDMYdrawing1030#Dummy layer for metal inductor
MDBLKdrawing1040#Dummy GATE and Metal Blocking layer
HVNWdrawing1050#NWELL for high voltage NMOS
HVPWdrawing1060#NWELL for high voltage PMOS
MCTdrawing1070#Metal Capacitor Top Layer
FLGTdrawing1080#Floating gate definition
FLGT2drawing1090#Floating gate 2definition
PLUGdrawing1100#Code dummy in MROM
FGCTdrawing1110#Connect point with floating gate
WLSP_SPACERdrawing1140#Word line space
MPOLdrawing1150#Memory poly
GSTIdrawing1160#Additional STI etching
ZNIPdrawing1170#Zener implant
HALIdrawing1180#Special drawing layer,for LDD implant into anti-well region
HRdrawing1190#High resistance resistor
HVPO_HVGOdrawing1200#High Voltage Poly
VTMNdrawing1220#2nd Medium VTN implant
VTMPdrawing1230#2nd Medium VTP implant
PESDdrawing1240#PESD implant
INAG2drawing1250#Active and poly ignore layer for LVS
BPIdrawing1260#PIP capacitor bottom plate implant
PCTdrawing1270#Poly capacitor top plate
NPIdrawing1280#N-type poly gate implant
INAGdrawing1300#Active and poly ignore layer for LVS
M1_TEXTdrawing1310#Metal1 text layer
M1_TEXTrdumm11311#Text layer
M2_TEXTdrawing1320#Metal2 text layer
M3_TEXTdrawing1330#Metal3 text layer
M4_TEXTdrawing1340#Metal4 text layer
M5_TEXTdrawing1350#Metal5 text layer
M6_TEXTdrawing1360#Metal6 text layer
M7_TEXTdrawing1370#Metal7 text layer
M8_TEXTdrawing1380#Metal8 text layer
M9_TEXTdrawing1390#Metal9 text layer
MVNWdrawing1410#Medium Voltage Nwell
MVPWdrawing1420#Medium Voltage Pwell
PMDMYdrawing1530#Identify Metal Fuse PMDMY
NLDD0drawing1560#NLDD implant for 1.8v device in Embeded Flash
MCEL_CELLdrawing1580#Memory Cell
PLDD0drawing1600#PLDD implant for 1.8v device in Embeded Flash
IPBoundarydrawing1610#For Flash IP
IPBoundaryrdumm11611#Customized IP boundary 1
IPBoundaryrdumm21612#Customized IP boundary 2
IPBoundarydummy16110#Photonics IP boundary
IPBoundarytext16195#IP_TEXT,CELL_TEXT
DUM_RFdrawing1620#RF device marking layer
DUM_RFdumrfd16211#Identify RF mod drain terminal
DUM_RFdumrfs16212#Extract metal space parameter of inductor for lvs
DUM_RFdumrfw16213#Extract metal width parameter of inductor for lvs
DUM_RFdumrfr16214#Extract inner diameter param of inductor for lvs
DUM_RFdumrfsym 16215#Symmetrical inductor marking layer
DUM_RFdumrfstd 16216#Standard inductor marking layer
DUM_RFlabass16231#Label layer for assura lvs
DUM_RFlabcal116232#Label layer 1 for calibre lvs
DUM_RFlabcal216233#Label layer 2 for calibre lvs
DUM_RFlabcal316234#Label layer 3 for calibre lvs
DUM_RFlabcal416235#Label layer 4 for calibre lvs
DUM_RFlabcal516236#Label layer 5 for calibre lvs
DUM_RFlabcal616237#Label layer 6 for calibre lvs
DUM_RFlabcal716238#Label layer 7 for calibre lvs
DUM_RFlabcal816239#Label layer 8 for calibre lvs
DUM_RFxrcblk16240#Dummy layer for calibre xrc extraction
DUM_VARdrawing1630#Varactor device marking layer
UDEFdrawing1680#special specified layer by customer
HVdrawing1700#HV region for 32V device
HVhv2417024#Marking layer for 24V device
IHVPWdrawing1710#Isolated HVPW
HDNWdrawing1720#High voltage DNW
MCB_MCT2drawing1730#Metal Capacitor Bottom layer
LMARKdrawing1740#for laster repairing machine alignment
CVTNdrawing1750#Cell VT impant for NMOS
CVTPdrawing1760#Cell VT impant for PMOS
LVIDdrawing1770#For lowpower device Vt implant
NWDEdrawing1780#NW Drain Extension Implant
PWDEdrawing1790#PW Drain Extension Implant
ESDT1drawing1800#ESD covering layer for Power Pin
ESDT2drawing1810#ESD covering layer for 5V tolerant
EPOLYdrawing1820#Emitter Poly
BPOLYdrawing1830#Base Poly
NPNEWdrawing1840#NPN Emitter window
NPNSCIdrawing1850#NPN Selective collector implant
NPNCOLLdrawing1860#NPN Collector implant
NPNdrawing1870#NPN open
ZNVTdrawing1880#Blockage of zero implant
CGCTdrawing1890#Control Gate Contact
BCIdrawing1900#Body Contact Implant
## As the layer-number of these layers beyond the scope of user-definable in virtuoso_5141,
## So you will not see these layers definition in .tf file.
ACT_DUMdrawing2060#dummy ACT layer
SDLdrawing2110#Special Device layer(for HV process)
GATE_DUMdrawing2120#dummy GATE layer
M1_DUMdrawing2310#dummy M1
M2_DUMdrawing2320#dummy M2
M3_DUMdrawing2330#dummy M3
M4_DUMdrawing2340#dummy M4
M5_DUMdrawing2350#dummy M5
M6_DUMdrawing2360#dummy M6
M7_DUMdrawing2370#dummy M7
M8_DUMdrawing2380#dummy M8
M9_DUMdrawing2390#dummy M9
SCHCTdrawing2410#Schottky Contact
你的第一个mapfile是用于ICC出GDS的，第二个是用于virtuoso读写gds用的。
ICC读tluplus文件是用的mapfile的格式应该是：
#Astro TF_maskNamVSITF_layername
polypoly
metal1metal1
...............
多谢多谢·
请问您一下：我现在只有tluplus文件，没有itf文件，然后check_tlu_plus得时候map文件一直报错，那要怎么修改呢?能把tluplus文件转化为itf吗?
报的错误是：Error: Layer "via1" (via1) exists in the MW-tech but not in the mapping AND ITF file. (TLUP-002)
打开itf文件看一下，via1的名字。你名字敲错了
没有itf文件，然后不知道错在哪里
tluplus用word打开，前面的有itf的内容。
你这个问题解决了吗?我也遇到同样的问题了，如果你已经知道解决办法，希望能讲解一下，谢谢！
map写错了，
再说 starxt版本不能高于icc，否则tluplus信息读不出来的
me too.
回复1# hongbutiao
感謝回覆