后端面试--每日一题（007）
使用一般的WLM （不是zero WLM，也不是按照物理位置算的DCT），DC是如何计算delay的?
难度：2
一条Timing path上的Delay有2部分组成，Cell Delay + NetDelay。
在ＤＣ中，NetDelay应该来说就是有ＷＬＭ中得到的，而Cell Delay就是根据WLM中得到的input Tran跟Cell 的output load通过查表得到Cell delay。
我还要补充下，lib的setup 和 hold的timing应该也要算在内吧
既然问的是如何使用WLM来计算延迟，那一定是net delay了，
其实这是一个小坑，看你知道不知道WLM是用来计算什么的延迟。
现在问题变得直接了，就是考你WLM的具体用法--如何计算出net的R和C的?
面试时，发现有些人对问题的理解不是很清楚，就干脆把相关的东西全倒出来，希望其中有一个是面试官想要的答案。这种做法应该很容易被看穿，正确的做法是，首先明白问的是什么，如果不明白的话，可以与面试官沟通，搞明白后再回答不迟。
WLM,首先是有一个LUT，多大面积对应多长的线长
然后有个参数，选择enclosed,segment 什么的，
两者可以确定采用多长的线长。
DC在计算延时的时候，主要根据输出的tansition 和net的RC值来计算。
output tansition是由驱动cell的input tansition和load通过查表得到的
而net的rc就要根据所选取的wrie load model来计算，计算时和输出的fanout决定
以smic13的smic13_wl10为例
wire_load("smic13_wl10") {
resistance: 8.5e-8;
capacitance: 1.5e-4;
area: 0.7;
slope: 66.667;
fanout_length(1,66.667);
根据fanout值，由fanout(1,66.667)可以得出互连线长度为66.667，然后根据resistance和capacitance计算出互连线电容为1.5e-4*66.667，互连线电阻为8.5e-8*66.667
，当然如果扇出值表中没有，就会用到slope，例如扇出为3时，此时估算的互连线长度为1*66.667+（3-1）*slope，再计算出RC值，然后DC由此计算net的延时。
不知道回答的对不对，呵呵
这个每日一题非常好，对我们面临找工作的人非常有帮助，我每天都等着看，呵呵，希望小编可以一直发下去
Wire Load Models
For timing analysis performed before placement and routing, Design Compiler must estimate the wire delays. The simplest estimation method is the wire load model, which gets a rough value for the total wire capacitance, based on the size of the chip and the fanout of the net. Larger chip sizes and larger fanouts are assumed to result in longer wires and more resistance and capacitance. Wire load models are not used in IC Compiler because accurate wire information is available from the layout database.
For logic synthesis, you should use Design Compiler with topographical technology, if available, because it produces better results than wire load models. However, if you are not using Design Compiler in topographical mode, you can use wire load models to estimate the capacitance, resistance, and area of nets before floorplanning or layout. The wire load models provided in the technology library define the fanout-to-length relationships.
Note:
Wire load models are used only with Design Compiler running in standard mode, not topographical mode. Design Compiler with topographical technology and IC Compiler have better wire estimation methods, so wire load models are not used with these tools.
With wire load models, Design Compiler estimates the wire lengths of pin-to-pin connections based on fanout count, and then uses those estimates to calculate the effects of cell placement and wire routing. Fanout is the total number of pins on the net, excluding the driver pin.
The wire load model is defined in the library specification. In Liberty library syntax, the wire_load group defines the wire loads. For more information, see the Library Compiler documentation.
Design Compiler determines which wire load model to use for a design according to the wire load model you define with the set_wire_load_model command, the wire load indicated by the technology library’s wire_load_selection group, or the wire load model identified by the default_wire_load attribute in the library, in that order. If none of these items are defined, no wire load model is used. and the net resistance, capacitance, and delay values are zero.
Net Capacitance, Resistance, and Area Calculation
To calculate the capacitance of a net, Design Compiler performs the following steps:
1.
Determines the fanout of the net.
2.
Looks up the length in the wire load model.
3.
Calculates the capacitance by multiplying the length by the capacitance coefficient in the wire load model.
Example
Suppose that a wire load model is defined as follows in the library:
wire_load("90x90") {
capacitance :2.0 ;/* C per unit-length */
resistance:100.0 ;/* R per unit-length */
area:0.5 ;/* net-area per unit-length */
slope:1.5 ;/* extrapolation slope */
fanout_length(1,1) ;/* fanout_length pairs */
fanout_length(2,2.2);
fanout_length(3,3.3);
fanout_length(4,4.4);
}
To determine lumped net capacitance, total net resistance, and the design area due to the net, Design Compiler multiplies the capacitance, resistance, and area scaling factors by the estimated wire length.
Design Compiler calculates the net fanout value as the total number of pins on the net excluding one driver pin. For example, on a net with 2 fanin pins and 3 fanout pins, the fanout value is
(2 + 3) - 1 = 4
It calculates the lumped net capacitance by multiplying of the estimated wire length by the capacitance factor 2.0. For a fanout value of 4, the last fanout_length defines the wire length as 4.4, resulting in a calculated lumped net capacitance of
2.0 * 4.4 = 8.8
It calculates the total net resistance by multiplying the estimated wire length by the resistance factor, yielding a value of
4.4 * 100.0 = 440.0
When calculating pin-to-pin RC delays, Design Compiler interprets the total net resistance on the basis of the current operating condition’s tree_type attribute.
Design Compiler calculates the net area by multiplying the estimated wire length by the area factor, yielding a value of
4.4 * .5 = 2.2
Design Compiler uses the net area to measure the impact of different optimization possibilities on the total design area of the chip. An accurate net area estimate guides Design Compiler in selecting the best optimization for minimizing area.
Design Compiler uses interpolation between and extrapolation beyond the library-defined wire load values.
其实我一直没有好好琢磨过WLM的概念，跟如何去计算 R & C。
7#的正确
如果大家欢迎，每日一题会坚持下去，应该有不少题目哪！
等到全部发完了，面试时，我都不知道该怎么问了，只好现编题目啦！
等到那时面试的兄弟姐妹，不知是杯具还是洗具。
哇，小编就是面试官啊，呵呵
看到楼上才知道，干活永远赚不了多少钱，我不停地回帖就是为了攒点资产，无奈还是只有几百元。
可是小编的钱我是回十年也赚不来。这就是做生意的，唉，小编应该是这里的No.1 了吧。羡慕中
这个很好啊！受教了！
不是啊，这里的第一是一个叫flatten的，有180多万信元了
弱弱问下，什么是LUT?
谢谢！
look up table,查表
学习了！
这一题好！
根据库中给的wire_load_model
根据面积选择wire_load_model
根据选择的wire_load_model.算连线长度，根据长度，得到电阻电容负载，然后算延时
受教了！多谢！
陈小编，请教一个问题；.lib文件里面有多个wlm，如：wl10、wl20、wl30等，怎么根据需要选择特定的wlm呢
wl10一般指的是10k门大小的模块对应的连线模型，其他wl20,wl30类似。你可以根据模块的大小选择相应的连线模型。
多谢
诺诺问下，fanout_length(1,66.667)如何得知互联线长度为66.667，（）里的1代表的什么呢?为什么要减去这个1呢?
再问个基础问题，10k门是多大?这个k是千的意思还是单位呢?，新手
k是千的意思，10K门就是10000门。
好棒
受教啦
学习了
good thing , thanks