自己手动写的Ram如何做逻辑综合，求大神们指教~~~~~

on chip ram 是memory compiler 生成的， RTL 写的都是flop

module ram256x4(
input
wire
clk,
input
wire
w_en,
input
wire
r_en,
input
wire [7:0]w_addr,
input
wire [7:0]r_addr,
input
wire [3:0]data_in,
outputreg[3:0]data_out
);
reg [3:0] mem[255:0];//定义一个二维的存储体
always@(posedge clk)//写数据
if(w_en)
mem[w_addr] <= data_in;
always@(posedge clk)//读数据
if(r_en)
data_out<= mem[r_addr];
endmodule
我是这么手动写的，结果dc综合后看网表时都是用寄存器搭建的，你的意思是用软件直接生成吗，那我为什么这么写综合不成ram?
求指教，谢谢

你这么写，综合出来就是寄存器搭建的。
如果要使用sram，需要用memory compiler生成，RTL设计再来调用，DC综合时使用SRAM的db文件作为hard block。

flop 搭建ram 太浪费了

moduleRom16x32(sclk,r_en,raddr,rdata);
inputwiresclk;
inputwirer_en;
inputwire[4:0]raddr;
outputreg[15:0]rdata;
reg[15:0]Rom[0:31];
//////
always@(posedge sclk)
if(r_en)
rdata<=Rom[raddr];
initial
begin
Rom[0]<= 16'b1000_1011_0100_1010;
Rom[1]<= 16'b0010_1010_0110_1011;
Rom[2]<= 16'b1110_1011_0100_1010;
Rom[3]<= 16'b1100_1011_0100_1000;
Rom[4]<= 16'b1000_1011_0110_1010;
Rom[5]<= 16'b1000_1011_0100_1001;
Rom[6]<= 16'b0000_1011_0100_1010;
Rom[7]<= 16'b1000_1011_0110_1010;
Rom[8]<= 16'b1010_1011_0111_1110;
Rom[9]<= 16'b0000_1011_0100_1010;
Rom[10]<=16'b1010_1011_0100_1100;
Rom[11]<=16'b1000_1011_0100_1010;
Rom[12]<=16'b0101_0101_1010_0101;
Rom[13]<=16'b1000_1011_0100_1011;
Rom[14]<=16'b1000_1011_0100_1010;
Rom[15]<=16'b1100_1011_0100_1010;
Rom[16]<=16'b1000_1011_0100_1010;
Rom[17]<=16'b1000_1011_0100_1010;
Rom[18]<=16'b1000_1011_0100_0010;
Rom[19]<=16'b1000_1011_0100_1010;
Rom[20]<=16'b1000_1011_0100_1011;
Rom[21]<=16'b1001_1011_0100_1010;
Rom[22]<=16'b1010_0101_1010_0101;
Rom[23]<=16'b1000_1011_0100_1010;
Rom[24]<=16'b1000_1101_1010_0101;
Rom[25]<=16'b1000_1011_0100_1010;
Rom[26]<=16'b1010_1011_0100_1010;
Rom[27]<=16'b1000_1011_0100_1011;
Rom[28]<=16'b1010_1011_0100_1010;
Rom[29]<=16'b1000_1011_0100_1010;
Rom[30]<=16'b1001_1011_0100_1010;
Rom[31]<=16'b1000_1011_0100_1110;
end
endmodule
这会综合成什么呢?我觉得也会用寄存器搭建的。怎么做才能综合出ROM?
求大神赐教~

你这个是不能综合的。下面的才行。
Rom会按照组合逻辑综合。也就是说芯片tape out之后，基本上很难改了。
小的rom就按照这种方式来做。如果是大的rom，还是用memory compiler 做吧。

moduleRom16x32(sclk,r_en,raddr,rdata);
inputwiresclk;
inputwirer_en;
inputwire[4:0]raddr;
outputreg[15:0]rdata;
reg[15:0]Rom;
//////
always@(posedge sclk)
if(r_en)
rdata<=Rom;
always @(*)
case(addr)
0:Rom = 16'b1000_1011_0100_1010;
1:ROm = 16'b0010_1010_0110_1011;
2:ROm = 16'b1110_1011_0100_1010;
3:ROm = 16'b1100_1011_0100_1000;
4:ROm = 16'b1000_1011_0110_1010;
5:ROm = 16'b1000_1011_0100_1001;
6:ROm = 16'b0000_1011_0100_1010;
7:ROm = 16'b1000_1011_0110_1010;
8:ROm = 16'b1010_1011_0111_1110;
9:ROm = 16'b0000_1011_0100_1010;
10:ROM = 16'b1010_1011_0100_1100;
11:ROM = 16'b1000_1011_0100_1010;
12:ROM = 16'b0101_0101_1010_0101;
13:ROM = 16'b1000_1011_0100_1011;
14:ROM = 16'b1000_1011_0100_1010;
15:ROM = 16'b1100_1011_0100_1010;
16:ROM = 16'b1000_1011_0100_1010;
17:ROM = 16'b1000_1011_0100_1010;
18:ROM = 16'b1000_1011_0100_0010;
19:ROM = 16'b1000_1011_0100_1010;
20:ROM = 16'b1000_1011_0100_1011;
21:ROM = 16'b1001_1011_0100_1010;
22:ROM = 16'b1010_0101_1010_0101;
23:ROM = 16'b1000_1011_0100_1010;
24:ROM = 16'b1000_1101_1010_0101;
25:ROM = 16'b1000_1011_0100_1010;
26:ROM = 16'b1010_1011_0100_1010;
27:ROM = 16'b1000_1011_0100_1011;
28:ROM = 16'b1010_1011_0100_1010;
29:ROM = 16'b1000_1011_0100_1010;
30:ROM = 16'b1001_1011_0100_1010;
31:ROM = 16'b1000_1011_0100_1110;
endcase
endmodule