PARA-075 (error) Could not resolve net

做PT的时候，用starRC提取的spef文件反标注到STA中，发现有些线网不能resolved，提示错误如下所示：
Information: Derived library resistance unit is 1.000000 Kohm (Time unit is 1 ns, and Capacitance unit is 1.000000 pF). (DES-028)
Error: Could not resolve net 'I210/net30740'.(PARA-075)
Error: Invalid capacitor (I0/DFF694/Q_reg:H02 0.0205587) on net I0/s_clock1:
Pin 'I0/DFF694/Q_reg/H02' is not connected to net (PARA-044)
Error: Invalid capacitor (I0/DFF709/Q_reg:H02 0.0266244) on net I0/s_clock1:
Pin 'I0/DFF709/Q_reg/H02' is not connected to net (PARA-044)
Error: Invalid capacitor (I0/DFF619/Q_reg:H02 0.0281775) on net I0/s_clock1:
Pin 'I0/DFF619/Q_reg/H02' is not connected to net (PARA-044)
Error: Invalid capacitor (I0/I6412/U1:N01 0.0404529) on net I0/s_clock1:
Pin 'I0/I6412/U1/N01' is not connected to net (PARA-044)
starRC提取出来的net却是icc产生的.v文件里头所没有的，没搞懂。
是我Icc 里头生成的.v文件不对么?先前有做过一次，是OK的，后来有修改过tcl，后就成这样了。
参考过http://bbs.eetop.cn/thread-319247-1-1.html，仍没法解决，各位大神请支招啊。
route流程：
set flow route
open_mw_lib $my_mw_lib
redirect /dev/null "remove_mw_cel -version_kept 0 route"
copy_mw_cel -from cts -to route
open_mw_cel route
#list_libs
#source scripts/common_optimization_settings_icc.tcl
#source scripts/common_placement_settings.tcl
#source scripts/common_post_cts_timing_settings.tcl
#source scripts/common_route_si_settings_zrt_icc.tcl
#report_constraint -all
all_ideal_nets
#all_high_fanout -nets -threshold 501
report_preferred_routing_direction
report_tlu_plus_files
check_legality
verify_pg_nets
preroute_standard_cells -remove_floating_pieces
verify_pg_nets
set_route_zrt_common_options-post_detail_route_redundant_via_insertion medium
set_route_zrt_detail_options-optimize_wire_via_effort_level medium
report_routing_rules; # report routing rules
report_route_opt_strategy; # report route_opt_stretegy
report_route_zrt_common_options; # Reports zrt common route options
report_route_zrt_global_options; # Reports zrt global route options
report_route_zrt_track_options; # Reports zrt route track assignment options
report_route_zrt_detail_options; # Reports zrt detail route options
route_opt -initial_route_only

route_opt -skip_initial_route
#route_opt -skip_initial_route -power
derive_pg_connection -power_net VDD -power_pin VDD -ground_net GND -ground_pin GND
derive_pg_connection -power_net VDD -ground_net GND -tie
verify_zrt_route
verify_lvs
route_zrt_eco
report_design_physical -route
#focal_opt -effort high -hold_endpoints all
redirect -tee ./timing/${flow}_timing.rpt { report_timing }
redirect -tee ./timing/${flow}_clock_tree.rpt { report_clock_tree -summary }
redirect -tee ./timing/${flow}_clock_timing.rpt { report_clock_timing -type skew}
redirect -tee ./timing/${flow}_qor.rpt {report_qor}
redirect -tee ./timing/${flow}_constraint { report_constraint -significant_digits 4-all}
#save_mw_cel -as route_opt_final
save_mw_cel
change_names -rules verilog -hierarchy -verbose
write_verilog\
-unconnected_ports \
-output_net_name_for_tie \
-wire_declaration \
-split_bus \
-no_tap_cells \
-no_corner_pad_cells\
-no_pad_filler_cells\
-no_core_filler_cells\
-no_flip_chip_bump_cells \
-no_pg_pin_only_cells \
./out/${top_design}.fm.v
#no split for sim
write_verilog\
-unconnected_ports \
-output_net_name_for_tie \
-wire_declaration \
-no_tap_cells \
-no_corner_pad_cells\
-no_pad_filler_cells\
-no_core_filler_cells\
-no_flip_chip_bump_cells \
-no_pg_pin_only_cells \
./out/${top_design}.pt.v
set_write_stream_options \
-child_depth 99 \
-map_layer${gdsout_map} \
-output_filling[list fill] \
-output_outdated_fill \
-keep_data_type \
-output_pin [list text geometry]
write_stream\
-lib_name $my_mw_lib\
-cells route\
-format gds ./out/${top_design}_lvs.gds

write -format verilog -hier -output out/{top_design} .v

顶起，ICC:201003，PT:201006，STAR:201006

没大神搭理啊，呼呼，再次顶起。
好像是因为我修改了tcl引起的，但就是不知道是哪一步引起的。starrc提取的spef，多了一个net，死活对不上。更多的是因为hierarchical的原因引起的，好像。
我把set_dont_touch [list I0/s_clock1]屏蔽掉之后，就仅剩下这个错误了。
Error: Could not resolve net 'I210/net30740'.(PARA-075)

修改了hierarchical的一个连接线结构，问题得以解决。

请问是怎么修改的?