一些后端方面的问题——版主继续带领大家积极讨论啊（共105题）

在国外一个网站上看到的一些问题，有些比较基础，有的跟以前有重叠的地方，但面试、工作时可能会碰到，发上来大家讨论一下，活跃一下气氛！热烈欢迎小编们带领大家共同进步啊！
Q1. Explain the flow of physical design and inputs and outputs for each step in flow.
Q2. Why higher metal layers are preferred for Vdd and Vss?
Q3. Why clock is not synthesized in DC?
Q4. Which layer is used for clock routing and why?
Q5. Which is more complicated when you have a 32 MHz and 512 MHz clock design?
Q6. Whether congestion is related to placement or routing?
Q7. What parameters (or aspects) differentiate Chip Design & Block level design?
Q8. What is wire load model?
Q9. What is transition? What if transition time is more?
Q10. What is track assignment?
Q11. What is tie-high and tie-low cells and where it is used
Q12. What is threshold voltage? How it affect timing?
Q13. What is the significance of negative slack?
Q14. What is the difference between synthesis and simulation?
Q15. What is the difference between core filler cells and metal fillers?
Q16. What is signal integrity? How it affects Timing?
Q17. What is SDC constraint file contains?
Q18. What is scan chain? What if scan chain not detached and reordered? Is it compulsory?
Q19. What is partial floor plan?
Q20. What is OPC, PSM?
Q21. What is negative slack ? How it affects timing?
Q22. What is metal density, metal slotting rule?
Q23. What is meant my 9 track, 12 track standard cells?
Q24. What corner cells contains?
Q25. What are types of routing?
Q26. What are the steps that you have done in the design flow?
Q27. What are the steps involved in designing an optimal pad ring?
Q28. What are the problems faced related to timing?
Q29. What are the common issues in floor plan?
Q30. What is logic optimization and give some methods of logic optimization.
Q31. What is LEF?
Q32. What is latency? Give the various latency types?
Q33. What is IR drop? How to avoid .how it affects timing?
Q34. What is hold problem? How can you avoid it?
Q35. What is grided and gridless routing?
Q36. What is floor plan and power plan?
Q37. What is ESD?
Q38. What is EM and it’s effect?
Q39. What is effective utilization and chip utilization?
Q40. What is each macro size and no. of standard cell count?
Q41. What is difference between normal buffer and clock buffer?
Q42. What is difference between HFN synthesis and CTS?
Q43. What is DEF?
Q44. What is cross talk? How can you avoid?
Q45. What is core and how you will decide w/h ratio for core?
Q46. What is content of lib, lef, sdc?
Q47. What is congestion?
Q48. What is cloning and buffering?
Q49. What is cell delay and net delay?
Q50. What is antenna effect? How it can be avoided?
Q51. What is a macro and standard cell?
Q52. What is a grid? Why we need different types of grids?
Q53. What is .lib, LEF, DEF, .tf?
Q54. What if hot spot found in some area of block? How you tackle this?
Q55. What are the Input needs for your design?
Q56. What are the input files will you give for primetime correlation?
Q57. What are the algorithms used while routing? Will it optimize wire length?
Q58. What are placement blockages?
Q59. What are high-Vt and low-Vt cells?
Q60. What are the common DFM issues?
Q61. What are delay models and what is the difference between them?
Q62. What are clock trees?
Q63. What are clock tree types?
Q64. Name few tools which you used for physical verification?
Q65. In your project what is die size, number of metal layers, technology, foundry, number of clocks?
Q66. In which layer do you prefer for clock routing and why?
Q67. If the routing congestion exists between two macros, then what will you do?
Q68. If lengthy metal layer is connected to diffusion and poly, then which one will affect by antenna problem?
Q69. If in your design has reset pin, then it’ll affect input pin or output pin or both?
Q70. How will you place the macros?
Q71. How will you decide the Pin location in block level design?
Q72. How will you decide the die size?
Q73. How to find total chip power?
Q74. How to find number of power pad and IO power pads?
Q75. How to decide number of pads in chip level design?
Q76. How to calculate core ring width, macro ring width and strap or trunk width?
Q77. How to calculate core ring and stripe widths?
Q78. How the width of metal and number of straps calculated for power and ground?
Q79. How slow and fast transition at inputs effect timing for gates?
Q80. How R and C values are affecting time?
Q81. How ohm (R), farad (C) is related to second (T)?
Q82. How much aspect ratio should be kept (or have you kept) and what is theutilization?
Q83. How many macros in your previous design?
Q84. How double spacing will avoid cross talk?
Q85. How do you place macros in a full chip design?
Q86. How did you do power planning?
Q87. How do you resolve the setup and hold time violation problem?
Q88. How did you handle the Clock in your design?
Q89. How delays vary with different PVT conditions? Show the graph.
Q90. How can you estimate area of block?
Q91. During power analysis, if you are facing IR drop problem, then how did you avoid?
Q92. Differentiate between a Hierarchical Design and flat design?
Q93. Define antenna problem and how did you resolve these problem?
Q94. After adding stripes also if you have hot spot, what do you do?
Q95. What is meant by scaling in VLSI design? Describe various effects of scaling.
Q96. What is meant by 90nm technology?
Q97. What is a transmission gate, and what is its typical use in VLSI?
Q98. What is ASIP?
Q99. What are the differences between gate array ASIC and cell based ASIC?
Q100. When you want the production in bulk amount which design style you prefer? Justify?
Q101. State the importance of Lithography in VLSI design?
Q102. Power Optimization Techniques for deep sub micron?
Q103. Define congestion in routing?
Q104. What do you mean by rip-up and re-routing?
Q105. What is Yield in fabrication process?

围观强势围观！

小编有问题可以提出来大家讨论。但是一下贴这么多出来，而且很多又是以前反复出现过的。
恐怕这也只能是围观。

确实是个问题，只是功力还不够，不知道深浅，有些对新人还是有一定的科普作用的，为保持完整性没有删掉。恳请各位大牛包括陈涛、icfbicfb等小编帮忙啊

好，慢慢来， 回答的好的，我来给奖励

这个好，新人学习的好东西。

感觉像面试题目似的

也来围观一下

这个贴，可以置顶吧，持续关注

求小编整理答案啊。
太经典了这个。

为方便大家讨论引用，特加入题号，共105题，每10题一组，欢迎大家积极提问和解答！

我靠，这么多，先MARK一个吧。LZ应该一个一个放嘛，这样大家才得讨论撒

很给力啊！

果然适合我们这种新人，好贴！

谢谢搂住

这么好的帖子，没有跟帖，太浪费了。既然大家都在等整理，那就让我来抛砖引玉好了，鉴于题目确实太多，就每十个为一组，给出我的答案，让后大家讨论好了。
Q1. Explain the flow of physical design and inputs and outputs for each step in flow.
答：这个问题，论坛中早有高人给出过答案了。http://bbs.eetop.cn/thread-444811-1-1.html
Q2. Why higher metal layers are preferred for Vdd and Vss?
答：1.上层金属资源比较充足，不像下层金属利用率那么高 2.上层金属厚度较厚适合大电流通过 3.EM能力不同，上层金属更加适合作为power布线来用。
Q3. Why clock is not synthesized in DC?
答：因为没有flip-flop的placement信息，synthesize不可能meet真正的skew target
Q4. Which layer is used for clock routing and why?
答：尽可能启用上层金属，如果最上面的几层的被电源占掉，就启用剩下能用的高层金属，因为clock是非常重要的部分，所以同样需要能通过大电流，且EM能力强的金属层。
Q5. Which is more complicated when you have a 32 MHz and 512 MHz clock design?
答：当然是512MHz的clock design更加复杂，因为频率高了，它的constrain也就更加的严格，就更加难以实现。
Q6. Whether congestion is related to placement or routing?
答：与routing有关
Q7. What parameters (or aspects) differentiate Chip Design & Block level design?
Chip design 有 I/O pads; block design 有 pins.
Chip design 能用可用的所有金属层; block design 一般不会用到所有金属层.
Chip 的形状一般都是长方形的; blocks 可以是长方形的也可以是 rectilinear的（不是那么规则的）.
Chip design 最终好要封装，而block design最终形成macro.
Q8. What is wire load model?
答：是估算net的R和C的模型，主要有zero wire load model，基于fanout的wire load model和基于物理位置的wire load model
Q9. What is transition? What if transition time is more?
答：transition就是斜率，当transition time 变大会使得速度变慢，且功耗增大
Q10. What is track assignment?
答：分配给每一条net一个特定的路线，奠定了实际金属的走线轨迹。其目的是为每一条金属走线提供最理想的走线方式，确保尽可能出现长且直的走线，尽可能减少via的数量。

没人理我，呵呵，自己顶自己，相信有后来者能受益，也相信以后会有大牛来指正。
Q11. What is tie-high and tie-low cells and where it is used
答：tie-high和tie-low是钳位cell用于ESD保护
Q12. What is threshold voltage? How it affect timing?
答：阈值电压就是门限电压，是实现电平跳变的极限值，高阈值电压对于对抗漏电流的问题是有好处的，但是带来的代价是高阈值电压会使电路变慢。所以需要综合考虑速度与功耗的需求。可以考虑在关键路径上使用低阈值电压来满足时序要求，在非关键路径上使用高阈值电压来满足对漏电流的控制。
Q13. What is the significance of negative slack?
答：出现negative slack就说明有了时序违反，会引起时序问题
Q14. What is the difference between synthesis and simulation?
答：synthesis的结果是得到netlist，simulation只是仿真过程
Q15. What is the difference between core filler cells and metal fillers?
答：core filler其实就是cell filler，目的是将well OD连成片；metal filler的目的只是为了满足metal density
Q16. What is signal integrity? How it affects Timing?
答：信号完整性是指信号在传输路径上的质量，主要的问题包括IR drop，EM，地弹，串扰，反射等等。会引起delay 增加，setup/hold violation等问题
Q17. What is SDC constraint file contains?
答：SDC中包含
1.工作环境相关命令：set_operation_conditions
2.线负载模型相关命令：set_wire_load_model, set_wire_load_modeetc.
3.系统接口相关命令：set_drive, set_load, set_input_transition, set_fanout_loadetc.
4.时序约束相关命令：这部分约束比较多，包括创建clock，generated clock以及clock group，设定input，output delay，uncertainty的指定，还有idea latency，network 等等
5.时序个例相关命令：set_false_path, set_multicycle_path, set_max/min_delay etc
6.设计约束相关命令：set_max_transition/capacitance/fanout, set_min_capacitance etc
7.逻辑赋值相关命令：set_case_analysis, set_logic_one, set_logic_dc, set_logic_zero etc
Q18. What is scan chain? What if scan chain not detached and reordered? Is it compulsory?
答：scan chain是用于DFT测试的。scan chain的reorder是必要的，这是因为在placement的过程中，timing-driven的算法会focus在timing violation上面，这就意味着会吧关键路径上的register pairs拉近，而不去考虑scan chain的连接，就会造成scan chain的route会很远或是绕来绕去，如果不做reorder，那么routing过程中就会出现congestion，并且functional speed的测试
Q19. What is partial floor plan?
答：这个问题没研究过，不知道是涉及partical power net placement blockage还是什么。
Q20. What is OPC, PSM?
答：为了增加曝光图案的真实性，增加了修正的mask，PSM是类似的另一种用于mask的技术，目的一样都是曝光后的图形接近layout的mask。涉及的DFM的内容，再深入的着实不懂。

继续顶自己，这一波题目真是不擅长，需高人指点了。
Q21. What is negative slack ? How it affects timing?
答：negative slack就意味着setup/hold violation，如果再tapout之后setup violation还存在，那么可以通过降低时钟频率的方式使得芯片正常工作，如果hold violation还存在就没有办法了，但是一般情况下hold simulation是在FF corner，HIGH voltage，Low temperature下进行的，所以如果运气好的话，可以通过用low voltage，High temperature，SS corner去测其他部分。为下次tapout做准备。
Q22. What is metal density, metal slotting rule?
答：IC导线是通过沉积+光刻、腐蚀来实现的，所以在整个wafer上需要沉积金属薄膜，基于wafer平坦度的考虑，这个直接关系到后续的工序的精确度和wafer的良率，所以有一定的metal density的要求。因为单位区域内的金属密度一般是在50%到80%之间，所以对较宽的金属走线，尤其是电源走线需要通过切割分布的方法实现密度要求，slotting就是其中的一种方法
Q23. What is meant my 9 track, 12 track standard cells?
答：因为standard cell pin基本上都是metal2连起来的，所以一般site width就是metal2的pitch，cell高度一般都是site width的整数倍，9倍高度，就是9 track standard cell，12倍高度，就是12 track standard cell。对于standard cell的选择，越大的一般都更快速，但是功耗越大。
Q24. What corner cells contains?
1） dummy bond pad 为了减小封装的难度和减小一些应力的效益 （不是必须的），因此corner pad两端最好空一些距离来bond wire，封装，否则封装有一定的难度，容易出问题
2） dummy poly ， 也是减小机械等效益，有一些ACtive， SP区域，不知道干啥的
Q25. What are types of routing?
答：global routing，track assignment，detail routing
Q26. What are the steps that you have done in the design flow?
答：data setup--design planning--placement--cts--routing--chipfinishing
Q27. What are the steps involved in designing an optimal pad ring?
答：1.插入corner PAD，再根据floorplan确定信号PAD的位置
2.根据core power的估算，计算出core power PAD的个数，根据信号IO的功耗和SSO计算IO power PAD。然后插入到信号IO PAD里面。
3.加入其它PAD，在不同的core 电压和不同的IO电压之前，power island之间，数字模拟电源之间加入power cut。加入power on control PAD，每个不同电源之间加入ESD，最后加入filler PAD填充PAD ring
Q28. What are the problems faced related to timing?
答：setup/hold violation, DRC violation.
Q29. What are the common issues in floor plan?
答：IR drop，congestion，timing violation etc
Q30. What is logic optimization and give some methods of logic optimization.
答：buffer sizing, cell sizing, level adjustment, dummy buffering etc

我来接着从31题回答一下吧
Q31. What is LEF?
（library exchange format）,叫库交换格式，它是描述库单元的物理属性，包括端口位置、层定义和通孔定义。它抽象了单元的底层几何细节，提供了足够的信息，以便允许布线器在不对内部单元约束来进行修订的基础上进行单元连接。包含了工艺的技术信息，如布线的层数、最小的线宽、线与线之间的最小距离以及每个被选用cell，BLOCK，PAD的大小和pin的实际位置。cell，PAD的这些信息由厂家提供的LEF文件给出，自己定制的BLOCK的LEF文件描述经ABSTRACT后生成，只要把这两个LEF文件整合起来就可以了。
Q32. What is latency? Give the various latency types?
Clock Latency就是从时钟源到时序期间时钟输入端的延时，包括source latency 和network latency，source latency是从时钟源到定义的port的latency, network latency是从定义的port到时序器件时钟输入端的latency.
Q33. What is IR drop? How to avoid .how it affects timing?
电压降，就是由于线上存在电阻，离供电端口越远的地方电压就偏离越大。做好power和电源IO可以有效控制电压降。电压降的存在会影响信号的传输速度，对setup有影响。
Q34. What is hold problem? How can you avoid it?
Hold violation就是信号没有保持足够的时间，信号跑得太快，插buffer可有效修hold。
Q35. What is grided and gridless routing?
基于网格的布线，就是在core上都是track的网格，布线要放到track上。
Q36. What is floor plan and power plan?
Floorplan就是布局规划，完成芯片面积、IP/memory的放置、Power mesh等的任务。Power plan就是做一些与电源、低功耗有关的规划吧，比如power mesh的数量和宽度、IO Power cell的位置、low power cell的插入，例如always on cells, power swich cell等。
Q37. What is ESD?
ESD的全名是Electrostatics Discharge的缩写，意为静电放电。其定义为，带有静电电荷（电子不足或过剩）的载体放电，产生电子流。一般来讲，一个充电的导体接近另一个导体时，就可能发生静电放电。至于原理和保护我就不罗嗦了，网上资料很多很详细。
Q38. What is EM and it’s effect?
电迁移，就是金属电子会随着电流的方向移动，时间长了会引起金属线分布不均匀，对信号的传输有影响，影响timing。
Q39. What is effective utilization and chip utilization?
标准单元面积占core面积的比率。
Q40. What is each macro size and no. of standard cell count?
没明白题干，求助高手！
/*本人IC菜鸟，有错误或不完整的地方希望高手来指正和补充，谢谢by tiwen*/

好东西，好详细

很早的时候发的帖子，我都忘了，当时小菜菜，不敢擅自发言啊，谢谢挖掘出来了啊

马克一下，留着慢慢研究
小编万分感谢啊

好东西，好详细

膜拜大神中。。

mark

现在小编已经是大牛了。不知道能否接下去回答一下?谢谢！

40题之后的答案呢，跪求

大神，后面题目的答案呢?

太多了，要慢慢看

Q13. What is the significance of negative slack?
答：出现negative slack就说明有了时序违反，会引起时序问题
关于Q13,我有点疑问.当PostRoute后,setup和hold都已经修过了.但是查看slack文件.里面还是有负值的,这也要修掉吗?怎样才能修过?