非ICG的clock_gate timing check问题
时间:10-02
整理:3721RD
点击:
由于工艺库不提供ICG单元,clock_gate是通过“latch+and”实现的,但用DC工具对该clock_gate的timing check遇到一些问题
首先,约束里设置了set_clock_gating_check命令,DC会查两条timing arc:
a、DFF/q(ck) ----> latch/en的timing arc(称为“a路径”)b、latch/q(ck)-----> and/a的timing arc(简称“b路径”)
DC工具在一般情况下会正常check上述两个路径,但遇到如下两个不理解的地方:
1、若clock_gate的输出时钟没有接任何DFF(后面接了一个或门),这个clock_gate的“b路径”不会检查,即便我设置了
set_clock_gating_check [get_cells**/latch]
set_clock_gating_check [get_cells**/and]
set_clock_gating_check [get_pins**/and/a(b)()]
set_clock_gating_check [get_clkclk_name]
这些命令都不起作用。
我后来有尝试在该clock_gate后加上一些DFF而不接或门,这个clock_gate的“b路径”就顺利check了。
2、“a路径”的hold检查也比较奇怪,由于用到的latch是高电平有效,所以在latch clk端加了INV,时钟周期是18ns,为什么时钟开始都加上了一个时钟周期呢?
Startpoint: clkgen_inst/clkgen_maindiv_inst/clkmux_inst/clk2_flop_d2_reg
(rising edge-triggered flip-flop clocked by clk_div)
Endpoint: clkgen_inst/clkgen_maindiv_inst/clkmux_inst/clkgate_clk2/latch_dont_touch_inst
(positive level-sensitive latch clocked by clk_div')
Path Group: clk_div
Path Type: min
PointFanoutTransIncrPath
------------------------------------------------------------------------------------
clock clk_div (rise edge)18.0018.00
clock network delay (ideal)0.0018.00
clkgen_inst/clkgen_maindiv_inst/clkmux_inst/clk2_flop_d2_reg/cp (dffs2x)
0.000.0018.00 r
clkgen_inst/clkgen_maindiv_inst/clkmux_inst/clk2_flop_d2_reg/q (dffs2x)
0.120.6718.67 r
clkgen_inst/clkgen_maindiv_inst/clkmux_inst/clk2_flop_d2 (net)
20.0018.67 r
clkgen_inst/clkgen_maindiv_inst/clkmux_inst/clkgate_clk2/en (clkgate_0)
0.0018.67 r
clkgen_inst/clkgen_maindiv_inst/clkmux_inst/clkgate_clk2/en (net)
0.0018.67 r
clkgen_inst/clkgen_maindiv_inst/clkmux_inst/clkgate_clk2/latch_dont_touch_inst/d (latch)
0.120.0018.67 r
data arrival time18.67
clock clk_div' (fall edge)18.0018.00
clock network delay (ideal)0.0018.00
clock uncertainty1.5019.50
clkgen_inst/clkgen_maindiv_inst/clkmux_inst/clkgate_clk2/latch_dont_touch_inst/cp (latch)
0.0019.50 f
library hold time-0.4619.04
data required time19.04
------------------------------------------------------------------------------------
data required time19.04
data arrival time-18.67
------------------------------------------------------------------------------------
slack (VIOLATED)-0.37
第一次用 latch+and 自己搭建clock_gate,望能有大神相助,小弟不胜感激!
首先,约束里设置了set_clock_gating_check命令,DC会查两条timing arc:
a、DFF/q(ck) ----> latch/en的timing arc(称为“a路径”)b、latch/q(ck)-----> and/a的timing arc(简称“b路径”)
DC工具在一般情况下会正常check上述两个路径,但遇到如下两个不理解的地方:
1、若clock_gate的输出时钟没有接任何DFF(后面接了一个或门),这个clock_gate的“b路径”不会检查,即便我设置了
set_clock_gating_check [get_cells**/latch]
set_clock_gating_check [get_cells**/and]
set_clock_gating_check [get_pins**/and/a(b)()]
set_clock_gating_check [get_clkclk_name]
这些命令都不起作用。
我后来有尝试在该clock_gate后加上一些DFF而不接或门,这个clock_gate的“b路径”就顺利check了。
2、“a路径”的hold检查也比较奇怪,由于用到的latch是高电平有效,所以在latch clk端加了INV,时钟周期是18ns,为什么时钟开始都加上了一个时钟周期呢?
Startpoint: clkgen_inst/clkgen_maindiv_inst/clkmux_inst/clk2_flop_d2_reg
(rising edge-triggered flip-flop clocked by clk_div)
Endpoint: clkgen_inst/clkgen_maindiv_inst/clkmux_inst/clkgate_clk2/latch_dont_touch_inst
(positive level-sensitive latch clocked by clk_div')
Path Group: clk_div
Path Type: min
PointFanoutTransIncrPath
------------------------------------------------------------------------------------
clock clk_div (rise edge)18.0018.00
clock network delay (ideal)0.0018.00
clkgen_inst/clkgen_maindiv_inst/clkmux_inst/clk2_flop_d2_reg/cp (dffs2x)
0.000.0018.00 r
clkgen_inst/clkgen_maindiv_inst/clkmux_inst/clk2_flop_d2_reg/q (dffs2x)
0.120.6718.67 r
clkgen_inst/clkgen_maindiv_inst/clkmux_inst/clk2_flop_d2 (net)
20.0018.67 r
clkgen_inst/clkgen_maindiv_inst/clkmux_inst/clkgate_clk2/en (clkgate_0)
0.0018.67 r
clkgen_inst/clkgen_maindiv_inst/clkmux_inst/clkgate_clk2/en (net)
0.0018.67 r
clkgen_inst/clkgen_maindiv_inst/clkmux_inst/clkgate_clk2/latch_dont_touch_inst/d (latch)
0.120.0018.67 r
data arrival time18.67
clock clk_div' (fall edge)18.0018.00
clock network delay (ideal)0.0018.00
clock uncertainty1.5019.50
clkgen_inst/clkgen_maindiv_inst/clkmux_inst/clkgate_clk2/latch_dont_touch_inst/cp (latch)
0.0019.50 f
library hold time-0.4619.04
data required time19.04
------------------------------------------------------------------------------------
data required time19.04
data arrival time-18.67
------------------------------------------------------------------------------------
slack (VIOLATED)-0.37
第一次用 latch+and 自己搭建clock_gate,望能有大神相助,小弟不胜感激!
自己顶一下
DFF使用下降沿抓过en后,再使用and来门控,只对and做clock gating check即可,好过用latch和and来搭建,DFF时序分析比latch方便。
使用DFF+and后,通过设置set_clock_gating_check [get_cells**/and] 命令来check AND门上的timing吗?
自己顶一下