请赐教 : encounter导出的gds导入virtuoso进行DRC时通不过？
时间：10-02
整理：3721RD
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我刚解决了一个问题，就是将encounter里的gds能够“完全”导入virtuoso能够显示.先给大家分享一下，希望能够给有相同难题的同仁带来一些帮助：
开始的时候encounter导GDS出来的时候有个streamout.map这个文件我以为是输出文件就没有管它，后来发现导入virtuoso里的metal层和via这些都不对。经过请教才发现encounter导GDS时的streamout.map文件是输入文件，而不是输出文件，所以我就按照virtuoso里的tf文件的定义改了层位置，再从encounter里导出GDS，这样在virtuoso里就可以发现metal层和via都是正确的。
我本以为这样就可以了，但是我在做DRC的时候确报错了。
错误信息如下：
Rule File Pathname: /home/cwg/cds/_SmicDR4P6P_cal018_mixlog_sali_p1mt6_1833.drc_
Minimum space between two NW regions with the same potential is 0.60um
Merge if space is less than 0.6um
Rule File Pathname: /home/cwg/cds/_SmicDR4P6P_cal018_mixlog_sali_p1mt6_1833.drc_
Minimum width of an M2 region is 0.28um
Rule File Pathname: /home/cwg/cds/_SmicDR4P6P_cal018_mixlog_sali_p1mt6_1833.drc_
Minimum space between two M2 regions is 0.28um
Rule File Pathname: /home/cwg/cds/_SmicDR4P6P_cal018_mixlog_sali_p1mt6_1833.drc_
Minimum width of an M3 region is 0.28um
Rule File Pathname: /home/cwg/cds/_SmicDR4P6P_cal018_mixlog_sali_p1mt6_1833.drc_
Minimum space between two M3 regions is 0.28um
Rule File Pathname: /home/cwg/cds/_SmicDR4P6P_cal018_mixlog_sali_p1mt6_1833.drc_
Minimum area of a M3 region is 0.20um
Rule File Pathname: /home/cwg/cds/_SmicDR4P6P_cal018_mixlog_sali_p1mt6_1833.drc_
Minimum width of an M4 region is 0.28um
Rule File Pathname: /home/cwg/cds/_SmicDR4P6P_cal018_mixlog_sali_p1mt6_1833.drc_
Minimum width of an M5 region is 0.28um
Rule File Pathname: /home/cwg/cds/_SmicDR4P6P_cal018_mixlog_sali_p1mt6_1833.drc_
Minimum space between two M5 regions is 0.28um
Rule File Pathname: /home/cwg/cds/_SmicDR4P6P_cal018_mixlog_sali_p1mt6_1833.drc_
Minimum space between two V1 is 0.26um
Rule File Pathname: /home/cwg/cds/_SmicDR4P6P_cal018_mixlog_sali_p1mt6_1833.drc_
Minimum space between two V2 is 0.26um
Rule File Pathname: /home/cwg/cds/_SmicDR4P6P_cal018_mixlog_sali_p1mt6_1833.drc_
Minimum space between two V3 is 0.26um
Rule File Pathname: /home/cwg/cds/_SmicDR4P6P_cal018_mixlog_sali_p1mt6_1833.drc_
Minimum space between two V4 is 0.26um
Rule File Pathname: /home/cwg/cds/_SmicDR4P6P_cal018_mixlog_sali_p1mt6_1833.drc_
Minimum/maximum size of a VT is 0.36um
Rule File Pathname: /home/cwg/cds/_SmicDR4P6P_cal018_mixlog_sali_p1mt6_1833.drc_
Minimum space between two VT is 0.35um
从错误信息来看，encounter在自动布线时via to via,metal to metal 和via to metal的间距都没有考虑，所以在DRC的时候就报了很多这样的错误。
请问是不是LEF文件（Rev 2.0, Date 02-08-2003 and Document TD-L018-BL-2001 Rev 2R）和DRC文件（Date: 2007/08/06）的版本不匹配?还是我在encounter里导出GDS前修改的streamout.map有问题呢?还是有别的原因呢?
下面是LEF文件的版本信息(1)，DRC的版本信息(2)，tf文件在层次上的定义(3)和我在encounter streamout时修改后的streamout.map文件(4)：
（1）：LEF版本信息
#******
# TECH LIB NAME: smic18
# TECH FILE NAME: techfile.cds
#
# RC values have been extracted from SMIC's Interconnect Capacitance
# Table, Rev 2.0, Date 02-08-2003 and Document TD-L018-BL-2001 Rev 2R
#
# Resistance and Capacitance Values
# ---------------------------------
# The LEF technology files included in this directory contain
# resistance and capacitance (RC) values for the purpose of timing
# driven place & route.Please note that the RC values contained in
# this tech file were created using the worst case interconnect models
# from the foundry and assume a full metal route at every grid location
# on every metal layer, so the values are intentionally very
# conservative. It is assumed that this technology file will be used
# only as a starting point for creating initial timing driven place &
# route runs during the development of your own more accurate RC
# values, tailored to your specific place & route environment. AS A
# RESULT, TIMING NUMBERS DERIVED FROM THESE RC VALUES MAY BE
# SIGNIFICANTLY SLOWER THAN REALITY.
#
# The RC values used in the LEF technology file are to be used only
# for timing driven place & route. Due to accuracy limitations,
# please do not attempt to use this file for chip-level RC extraction
# in conjunction with your sign-off timing simulations. For chip-level
# extraction, please use a dedicated extraction tool such as HyperExtract,
# starRC or Simplex, etc.
#
# $Id: smic18_6lm.lef,v 1.4 2003-03-10 18:30:04-08 wching Exp $
#
#******
VERSION 5.2 ;
（2）：DRC的版本信息：
//$Author: Karen Kang
//$Revision: 1.1
//$Date: 2007/08/06 01:03:59 $
//=================================================================================
//||
//|0.18um 1P6M Calibre DRC rule file for|
//||
//|SMIC:0.18um LOGIC 1P6M Salicide 1.8V/3.3V Design Rule|
//|Doc. No.:TD-LO18-DR-2001Rev.: 4 T|
//||
//|SMIC:0.18um Mixed-Signal 1P6M Salicide 1.8V/3.3V Design Rule |
//|Doc. No.:TD-MM18-DR-2001Rev.: 6 P|
//||
//|SMIC DSD Technologies|
(3):tf文件在层次上的定义
( M161M1)
( M262M2)
( M363M3)
( M464M4)
( M565M5)
( M666M6)
( V170V1)
( V271V2)
( V372V3)
( V473V4)
( V574V5)
( OPCBA100OPCBA)
( OPCBP101OPCBP)
( OPCBM102OPCBM)
( M1TXT141M1TXT)
( M2TXT142M2TXT)
( M3TXT143M3TXT)
( M4TXT144M4TXT)
( M5TXT145M5TXT)
( M6TXT146M6TXT)
(4)：在encounter streamout时修改后的streamout.map文件
METAL1NET610
METAL1SPNET610
METAL1PIN610
METAL1LEFPIN610
METAL1FILL610
METAL1VIA610
METAL1VIAFILL610
METAL1LEFOBS610
NAMEMETAL1/NET1410
NAMEMETAL1/SPNET1410
NAMEMETAL1/PIN1410
NAMEMETAL1/LEFPIN1410
VIA12FILL700
VIA12VIA700
VIA12VIAFILL700
METAL2NET620
METAL2SPNET620
METAL2PIN620
METAL2LEFPIN620
METAL2FILL620
METAL2VIA620
METAL2VIAFILL620
METAL2LEFOBS620
NAMEMETAL2/NET1420
NAMEMETAL2/SPNET1420
NAMEMETAL2/PIN1420
NAMEMETAL2/LEFPIN1420
VIA23FILL710
VIA23VIA710
VIA23VIAFILL710
METAL3NET630
METAL3SPNET630
METAL3PIN630
METAL3LEFPIN630
METAL3FILL630
METAL3VIA630
METAL3VIAFILL630
METAL3LEFOBS630
NAMEMETAL3/NET1430
NAMEMETAL3/SPNET143 0
NAMEMETAL3/PIN1430
NAMEMETAL3/LEFPIN1430
VIA34FILL720
VIA34VIA720
VIA34VIAFILL720
METAL4NET640
METAL4SPNET640
METAL4PIN640
METAL4LEFPIN640
METAL4FILL640
METAL4VIA640
METAL4VIAFILL64 0
METAL4LEFOBS640
NAMEMETAL4/NET144 0
NAMEMETAL4/SPNET1440
NAMEMETAL4/PIN1440
NAMEMETAL4/LEFPIN1440
VIA45FILL730
VIA45VIA730
VIA45VIAFILL730
METAL5NET650
METAL5SPNET650
METAL5PIN650
METAL5LEFPIN650
METAL5FILL650
METAL5VIA650
METAL5VIAFILL650
METAL5LEFOBS650
NAMEMETAL5/NET1450
NAMEMETAL5/SPNET1450
NAMEMETAL5/PIN1450
NAMEMETAL5/LEFPIN1450
VIA56FILL740
VIA56VIA740
VIA56VIAFILL740
METAL6NET660
METAL6SPNET660
METAL6PIN660
METAL6LEFPIN660
METAL6FILL660
METAL6VIA66 0
METAL6VIAFILL660
METAL6LEFOBS660
NAMEMETAL6/NET1460
NAMEMETAL6/SPNET1460
NAMEMETAL6/PIN1460
NAMEMETAL6/LEFPIN1460
NAMECOMP1010
COMPALL1020
DIEAREAALL1120
大家看看究竟是什么原因呢?
是map文件修改后又问题呢?还是encounter里用的lef文件和virtuoso里用的tf文件版本不匹配（或者说是lef文件rule不全）呢?
开始的时候encounter导GDS出来的时候有个streamout.map这个文件我以为是输出文件就没有管它，后来发现导入virtuoso里的metal层和via这些都不对。经过请教才发现encounter导GDS时的streamout.map文件是输入文件，而不是输出文件，所以我就按照virtuoso里的tf文件的定义改了层位置，再从encounter里导出GDS，这样在virtuoso里就可以发现metal层和via都是正确的。
我本以为这样就可以了，但是我在做DRC的时候确报错了。
错误信息如下：
Rule File Pathname: /home/cwg/cds/_SmicDR4P6P_cal018_mixlog_sali_p1mt6_1833.drc_
Minimum space between two NW regions with the same potential is 0.60um
Merge if space is less than 0.6um
Rule File Pathname: /home/cwg/cds/_SmicDR4P6P_cal018_mixlog_sali_p1mt6_1833.drc_
Minimum width of an M2 region is 0.28um
Rule File Pathname: /home/cwg/cds/_SmicDR4P6P_cal018_mixlog_sali_p1mt6_1833.drc_
Minimum space between two M2 regions is 0.28um
Rule File Pathname: /home/cwg/cds/_SmicDR4P6P_cal018_mixlog_sali_p1mt6_1833.drc_
Minimum width of an M3 region is 0.28um
Rule File Pathname: /home/cwg/cds/_SmicDR4P6P_cal018_mixlog_sali_p1mt6_1833.drc_
Minimum space between two M3 regions is 0.28um
Rule File Pathname: /home/cwg/cds/_SmicDR4P6P_cal018_mixlog_sali_p1mt6_1833.drc_
Minimum area of a M3 region is 0.20um
Rule File Pathname: /home/cwg/cds/_SmicDR4P6P_cal018_mixlog_sali_p1mt6_1833.drc_
Minimum width of an M4 region is 0.28um
Rule File Pathname: /home/cwg/cds/_SmicDR4P6P_cal018_mixlog_sali_p1mt6_1833.drc_
Minimum width of an M5 region is 0.28um
Rule File Pathname: /home/cwg/cds/_SmicDR4P6P_cal018_mixlog_sali_p1mt6_1833.drc_
Minimum space between two M5 regions is 0.28um
Rule File Pathname: /home/cwg/cds/_SmicDR4P6P_cal018_mixlog_sali_p1mt6_1833.drc_
Minimum space between two V1 is 0.26um
Rule File Pathname: /home/cwg/cds/_SmicDR4P6P_cal018_mixlog_sali_p1mt6_1833.drc_
Minimum space between two V2 is 0.26um
Rule File Pathname: /home/cwg/cds/_SmicDR4P6P_cal018_mixlog_sali_p1mt6_1833.drc_
Minimum space between two V3 is 0.26um
Rule File Pathname: /home/cwg/cds/_SmicDR4P6P_cal018_mixlog_sali_p1mt6_1833.drc_
Minimum space between two V4 is 0.26um
Rule File Pathname: /home/cwg/cds/_SmicDR4P6P_cal018_mixlog_sali_p1mt6_1833.drc_
Minimum/maximum size of a VT is 0.36um
Rule File Pathname: /home/cwg/cds/_SmicDR4P6P_cal018_mixlog_sali_p1mt6_1833.drc_
Minimum space between two VT is 0.35um
从错误信息来看，encounter在自动布线时via to via,metal to metal 和via to metal的间距都没有考虑，所以在DRC的时候就报了很多这样的错误。
请问是不是LEF文件（Rev 2.0, Date 02-08-2003 and Document TD-L018-BL-2001 Rev 2R）和DRC文件（Date: 2007/08/06）的版本不匹配?还是我在encounter里导出GDS前修改的streamout.map有问题呢?还是有别的原因呢?
下面是LEF文件的版本信息(1)，DRC的版本信息(2)，tf文件在层次上的定义(3)和我在encounter streamout时修改后的streamout.map文件(4)：
（1）：LEF版本信息
#******
# TECH LIB NAME: smic18
# TECH FILE NAME: techfile.cds
#
# RC values have been extracted from SMIC's Interconnect Capacitance
# Table, Rev 2.0, Date 02-08-2003 and Document TD-L018-BL-2001 Rev 2R
#
# Resistance and Capacitance Values
# ---------------------------------
# The LEF technology files included in this directory contain
# resistance and capacitance (RC) values for the purpose of timing
# driven place & route.Please note that the RC values contained in
# this tech file were created using the worst case interconnect models
# from the foundry and assume a full metal route at every grid location
# on every metal layer, so the values are intentionally very
# conservative. It is assumed that this technology file will be used
# only as a starting point for creating initial timing driven place &
# route runs during the development of your own more accurate RC
# values, tailored to your specific place & route environment. AS A
# RESULT, TIMING NUMBERS DERIVED FROM THESE RC VALUES MAY BE
# SIGNIFICANTLY SLOWER THAN REALITY.
#
# The RC values used in the LEF technology file are to be used only
# for timing driven place & route. Due to accuracy limitations,
# please do not attempt to use this file for chip-level RC extraction
# in conjunction with your sign-off timing simulations. For chip-level
# extraction, please use a dedicated extraction tool such as HyperExtract,
# starRC or Simplex, etc.
#
# $Id: smic18_6lm.lef,v 1.4 2003-03-10 18:30:04-08 wching Exp $
#
#******
VERSION 5.2 ;
（2）：DRC的版本信息：
//$Author: Karen Kang
//$Revision: 1.1
//$Date: 2007/08/06 01:03:59 $
//=================================================================================
//||
//|0.18um 1P6M Calibre DRC rule file for|
//||
//|SMIC:0.18um LOGIC 1P6M Salicide 1.8V/3.3V Design Rule|
//|Doc. No.:TD-LO18-DR-2001Rev.: 4 T|
//||
//|SMIC:0.18um Mixed-Signal 1P6M Salicide 1.8V/3.3V Design Rule |
//|Doc. No.:TD-MM18-DR-2001Rev.: 6 P|
//||
//|SMIC DSD Technologies|
(3):tf文件在层次上的定义
( M161M1)
( M262M2)
( M363M3)
( M464M4)
( M565M5)
( M666M6)
( V170V1)
( V271V2)
( V372V3)
( V473V4)
( V574V5)
( OPCBA100OPCBA)
( OPCBP101OPCBP)
( OPCBM102OPCBM)
( M1TXT141M1TXT)
( M2TXT142M2TXT)
( M3TXT143M3TXT)
( M4TXT144M4TXT)
( M5TXT145M5TXT)
( M6TXT146M6TXT)
(4)：在encounter streamout时修改后的streamout.map文件
METAL1NET610
METAL1SPNET610
METAL1PIN610
METAL1LEFPIN610
METAL1FILL610
METAL1VIA610
METAL1VIAFILL610
METAL1LEFOBS610
NAMEMETAL1/NET1410
NAMEMETAL1/SPNET1410
NAMEMETAL1/PIN1410
NAMEMETAL1/LEFPIN1410
VIA12FILL700
VIA12VIA700
VIA12VIAFILL700
METAL2NET620
METAL2SPNET620
METAL2PIN620
METAL2LEFPIN620
METAL2FILL620
METAL2VIA620
METAL2VIAFILL620
METAL2LEFOBS620
NAMEMETAL2/NET1420
NAMEMETAL2/SPNET1420
NAMEMETAL2/PIN1420
NAMEMETAL2/LEFPIN1420
VIA23FILL710
VIA23VIA710
VIA23VIAFILL710
METAL3NET630
METAL3SPNET630
METAL3PIN630
METAL3LEFPIN630
METAL3FILL630
METAL3VIA630
METAL3VIAFILL630
METAL3LEFOBS630
NAMEMETAL3/NET1430
NAMEMETAL3/SPNET143 0
NAMEMETAL3/PIN1430
NAMEMETAL3/LEFPIN1430
VIA34FILL720
VIA34VIA720
VIA34VIAFILL720
METAL4NET640
METAL4SPNET640
METAL4PIN640
METAL4LEFPIN640
METAL4FILL640
METAL4VIA640
METAL4VIAFILL64 0
METAL4LEFOBS640
NAMEMETAL4/NET144 0
NAMEMETAL4/SPNET1440
NAMEMETAL4/PIN1440
NAMEMETAL4/LEFPIN1440
VIA45FILL730
VIA45VIA730
VIA45VIAFILL730
METAL5NET650
METAL5SPNET650
METAL5PIN650
METAL5LEFPIN650
METAL5FILL650
METAL5VIA650
METAL5VIAFILL650
METAL5LEFOBS650
NAMEMETAL5/NET1450
NAMEMETAL5/SPNET1450
NAMEMETAL5/PIN1450
NAMEMETAL5/LEFPIN1450
VIA56FILL740
VIA56VIA740
VIA56VIAFILL740
METAL6NET660
METAL6SPNET660
METAL6PIN660
METAL6LEFPIN660
METAL6FILL660
METAL6VIA66 0
METAL6VIAFILL660
METAL6LEFOBS660
NAMEMETAL6/NET1460
NAMEMETAL6/SPNET1460
NAMEMETAL6/PIN1460
NAMEMETAL6/LEFPIN1460
NAMECOMP1010
COMPALL1020
DIEAREAALL1120
大家看看究竟是什么原因呢?
是map文件修改后又问题呢?还是encounter里用的lef文件和virtuoso里用的tf文件版本不匹配（或者说是lef文件rule不全）呢?
eetop
莫非这个问题真的很棘手?
现在都愁死我了。
导入的时候 是要把设计 core pad 导入3次吗
再试试吧 我也没过 这个
在foundry给的库文件中，应该就有map file的，我记得好像有两个map file，应该与tech file在一个directory。
从Encounter导出gds时，用的是lef-to-gds的map。你根据tf改得map file可能不太一样。
因为很久没有用过encounter，所以只是根据经验给一个建议哈。你可以先查查看。
再试试吧 我也没过 这个
顶起来，大神们在哪里?求解答啊
顶起来，大神们在哪里?求解答啊
厉害厉害，原来这个streamout文件是输入文件，终于搞清楚了
请问如果用encounter生成的GDS文件的drc错误很多，是因为在用encounter进行布局布线时的LEF文件用的和MERGE FILE版本不对应吗?还是说是软件本身布局出来就有错误