CMOS_IC_Layout_Concepts__Methodologies__and_Tools(by Dan Clein)
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CMOS_IC_Layout_Concepts__Methodologies__and_Tools(by Dan Clein)
CMOS IC LAYOUT Concepts, Methodologies, and Tools
Dan Clein
Technical Contributor: Gregg Shimokura
Copyright © 2000 by Butterworth–Heinemann
Preface
Acknowledgmentsxvii ...........................................
1 Introduction1 ..................................................
2 Schematic fundamentals7 .............................
3 Layout design22 ...............................................
4 Layout design flows68 .....................................
5 Advanced techniques for specialized
building-block layout design91 ..........................
6 Advanced techniques for building-block
interconnect layout design137 .............................
7 Layout design techniques to address
electrical characteristics154 ................................
8 Layout considerations due to process
constraints183 .......................................................
9 Layout design techniques in an
uncertain environment201 ....................................
10 Computer-aided design (CAD) tools for
layout216 ................................................................
Appendix A Audit checklists245 ..........................
Appendix B Database management249 ..............
Appendix C Scheduling254 ..................................
Index257 .................................................................
作者的话
Most textbooks on VLSI cover circuit design techniques or algorithms for CAD tools but none of them are explaining extensively IC Layout challenges. For today's industry, with so many new tools, platforms, methodologies, and design styles being developed all the time, a more unified format is needed. Now here it is, and is for more readers that you may think:
Students studying VLSI Design need a comprehensive textbook for IC Layout so their projects can be actually manufactured... Students studying Computer Engineering or Science and tools for VLSI need a book to help them understand the physical limitations from processing and design... IC layout designers around the world need a detailed training curriculum that covers more than just one type of layout... Design engineers need a book that can help them to understand the layout concepts so their designs can be more realistic and easier to implement... Software developers need a source of information beyond "clean room" specifications, they need a users voice with the specific industry language... Technical marketing and sales people need a dictionary to understand the language and the concepts required by their customers when they sale software and their own design teams when they sell a product...
But a book about layout is not complete if there are no color graphics. The problem is that colored pages inside a black and white book is very expensive and would have raised the price of our book. We wanted to make this book as affordable as possible so together with the publishers we decided to offer you a solution, a CD-ROM with additional color pictures. So, you will find in the CD-ROM attached all the color files that we prepared for your edification. But this is not all; we included a full demo version of L-Edit, from Tanner Research Inc. The demo content includes the entire Tanner tools demo so is useful for a new designer or student to try each of them. From our point of view is a tremendous opportunity for a reader to try as he/she learns about each topic. The demo provides access to "danclein" library so once you learned how to open the library all our secrets will be in your hands.
In the near future, we will try to build a web site that can be used as questions and answer place.
Please send us Email at cometic@ieee.org for any enquiry.
We hope that you will enjoy reading our book at list as much as we enjoyed writing it！
Dan Clein & Gregg Shimokura
"本书以循序渐进、深入浅出的方式，系统地介绍了CMOS 集成电路版图设计的基本概念、设计理念和各种方法技巧。全书共分10章，阐述了版图设计技术的基本概念和设计理念，当今流行的几种基本设计流程，专用模块的版图设计技巧，版图设计的高级技术和深层次概念，版图设计的基本工具类型，工具的特性和典型用法。与其他IC设计教程相比，本书注重理论与工程实践的结合，书中提供了大量实例来帮助读者正确理解版图设计的基本概念和关键设计理念，生动形象，简明易懂，可读性强。.
无论对版图设计工程师，还是对电路设计工程师、CAD人员、学习IC设计的学生，本书都是一本非常不错的参考指南和培训教程"
PREFACE
PREFACE:
PART ONE: THE BASICS
Where does layout design fit in the overall chip development process? Chapter 1
gives a nontechnical overview of the entire process so that we can understand the
layout designer’s role.
The mandate of an IC layout designer is to create the layout masks of
various portions of a chip in compliance with engineering drawings, netlist or
simulation results, and process design rules. To be capable of understanding
and respecting engineering drawings, the designer needs to understand basic
electricity rules and all the concepts related to the layout of gates. This will be
covered in Chapter 2.
Chapter 3 describes the manufacturing process and definition of layers. After
we understand how the layers are coordinated to generate devices and connectivity,
we learn about design rules. These are the manufacturing rules that must
be followed to ensure that the chip can be reliably manufactured. The process
engineers determine the minimum manufacturing grid, polygon, minimum distance
between layers, etc. The design rules are the rules that are the factor, which
together with the engineering drawings, netlist, etc., will fundamentally decide
the architecture of the chip.
PART TWO: LAYOUT STYLES
If a Layout Designer does not respect design requirements, the chip won’t work.
If the design rules are not respected, then the chip may not make it out of the prototyping
phase. The art of a good layout designer is to combine both, while taking
into consideration all the other aspects of a normal project: time to finish, final
size, quality, and so on. . . .
None of the chips just mentioned can claim that they are made up of only
one type of design style these days, so in Chapter 5 we talk about specialization
in design. We discuss full custom, standard cells, gate arrays, and other types of
techniques used in today’s ICs and the advantages and disadvantage of each type.
We talk about various techniques and methodologies used in complicated chips
for specific applications. The list is long, but some of them are clock generators,
datapath or register files, I/O cells, and memory types. We end the chapter with
chip finishing techniques.
PART THREE: ADVANCED TOPICS
The topic of Chapter 6 is related to the requirements of big chips for adequate connectivity
and power routing. We learn about methodologies to address all these
and discuss placement impact to routing, floorplanning techniques and results,
preplanned signals, etc.
Chapter 7 assumes that we know the basics and we start dealing with analog
problems, such as capacitors, electromigration, and 45-degree layout, to mention
Special process requirements are explained in Chapter 8. Learning about slits
in wide metals, step coverage, latch-up, and special design rules is possible now
that we understand even the most complicated process rules.
When the environment is uncertain, meaning that the process is not defined
yet or the design not 100 percent simulated, the layout designer has to face new
challenges. That’s why, in Chapter 9, we learn about contacts as cells, test pads,
spare logic gates and spare lines, and laying out a circuit with changes in mind.
PART FOUR: TOOLS OF THE TRADE
Perhaps the most exciting chapter is Chapter 10. This chapter analyzes various
EDA layout design tools required to face the challenges of any kind of layout
design. From crude polygon generation to place-and-route, from generators and
silicon compilers to verification tools, from plotting devices and software to transfer
formats, we try to show you a path through this maze of names, concepts,
methodologies, and usage. This chapter does not try to rate or recommend specific
tools, but it does try to enlighten the novice user about the choices in the marketplace
and how these tools might be adapted to different methodologies, and
vice versa.
This book is intended to help you protect yourself in a downpour of complicated
design methodologies pitched by EDA vendors, a world in which the
names of companies and tools change all the time, the hot topic each year is different,
and every year pundits at the Design Automation Conference are announcing
new catastrophes and solutions.
For example, first the machine was too small (CALMA). Then UNIX came
along and more memory was needed. Place-and-route appeared, along with
verification tools, extraction tools, and new terms like Deep Sub-Micron (DSM),
and so on. Even if the tools are solving most of today’s problems the market
requirements (prices) are always generating new “unsolved mysteries.”
This book is meant to help you prepare to understand the basic and
advanced concepts, and to learn how to analyze new methodologies and to understand
the philosophy of new tools. I hope that it will be useful for all of you, and
I will be more than happy to receive your comments. Please write me at the
following address:
Dan Clein
826 Riddell Avenue North
Ottawa, Ontario
Canada
K2A 2V9
cometic@ieee.org
only a few.
"本书以循序渐进、深入浅出的方式，系统地介绍了CMOS 集成电路版图设计的基本概念、设计理念和各种方法技巧。全书共分10章，阐述了版图设计技术的基本概念和设计理念，当今流行的几种基本设计流程，专用模块的版图设计技巧，版图设计的高级技术和深层次概念，版图设计的基本工具类型，工具的特性和典型用法。与其他IC设计教程相比，本书注重理论与工程实践的结合，书中提供了大量实例来帮助读者正确理解版图设计的基本概念和关键设计理念，生动形象，简明易懂，可读性强。.
无论对版图设计工程师，还是对电路设计工程师、CAD人员、学习IC设计的学生，本书都是一本非常不错的参考指南和培训教程"
layout也要看
支持！
Thanks！
CMOS_IC_Layout_Concepts__Methodologies__and_Tools
谢谢谢谢谢谢
好啊，支持小编
顶，
very good
thanks
thank you