calibre lvs问题 ，请高手进，求教

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##C A L I B R ES Y S T E M##
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##L V SR E P O R T##
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REPORT FILE NAME:2.lvs.report
LAYOUT NAME:/home/cds/edalab/2.sp ('2')
SOURCE NAME:/home/cds/edalab/2.src.net ('2')
RULE FILE:/home/cds/edalab/_1830AN18BA_CAL_3M_270.lvs_
CREATION TIME:Tue Dec 15 20:47:54 2015
CURRENT DIRECTORY:/home/cds/edalab
USER NAME:cds
CALIBRE VERSION:v2008.1_20.15Tue Mar 4 19:02:13 PST 2008

OVERALL COMPARISON RESULTS

##########################
# ###
##NOT COMPARED#
# ###
##########################

Error:Different numbers of ports.
Error:Power or ground net missing.

**************************************************************************************************************
CELLSUMMARY
**************************************************************************************************************
ResultLayoutSource
------------------------------------
NOT COMPARED22

**************************************************************************************************************
LVS PARAMETERS
**************************************************************************************************************

o LVS Setup:
LVS COMPONENT TYPE PROPERTYphy_comp element comp
LVS COMPONENT SUBTYPE PROPERTYphy_model
LVS PIN NAME PROPERTYphy_pin
LVS POWER NAME"vdd"
LVS GROUND NAME"vss"
LVS CELL SUPPLYNO
LVS RECOGNIZE GATESALL
LVS IGNORE PORTSNO
LVS CHECK PORT NAMESYES
LVS IGNORE TRIVIAL NAMED PORTSNO
LVS BUILTIN DEVICE PIN SWAPNO
LVS ALL CAPACITOR PINS SWAPPABLENO
LVS DISCARD PINS BY DEVICENO
LVS SOFT SUBSTRATE PINSNO
LVS INJECT LOGICYES
LVS EXPAND UNBALANCED CELLSYES
LVS EXPAND SEED PROMOTIONSNO
LVS PRESERVE PARAMETERIZED CELLSNO
LVS GLOBALS ARE PORTSYES
LVS REVERSE WLNO
LVS SPICE PREFER PINSNO
LVS SPICE SLASH IS SPACEYES
LVS SPICE ALLOW FLOATING PINSYES
// LVS SPICE ALLOW INLINE PARAMETERS
LVS SPICE ALLOW UNQUOTED STRINGSNO
LVS SPICE CONDITIONAL LDDYES
LVS SPICE CULL PRIMITIVE SUBCIRCUITSNO
LVS SPICE IMPLIED MOS AREANO
// LVS SPICE MULTIPLIER NAME
LVS SPICE OVERRIDE GLOBALSNO
LVS SPICE REDEFINE PARAMNO
LVS SPICE REPLICATE DEVICESYES
LVS SPICE STRICT WLNO
// LVS SPICE OPTION
LVS STRICT SUBTYPESNO
LAYOUT CASEYES
SOURCE CASEYES
LVS COMPARE CASENO
LVS DOWNCASE DEVICENO
LVS REPORT MAXIMUM50
LVS PROPERTY RESOLUTION MAXIMUM32
// LVS SIGNATURE MAXIMUM
LVS FILTER UNUSED OPTIONAB O RB RC RD RE RG
// LVS REPORT OPTION
LVS REPORT UNITSYES
// LVS NON USER NAME PORT
// LVS NON USER NAME NET
// LVS NON USER NAME INSTANCE
// Device Type Map
LVS DEVICE TYPEPMOS "pch_eprom_5p0v_pgm" SOURCE LAYOUT
LVS DEVICE TYPENMOS "nch_svt_5p0v" SOURCE LAYOUT
LVS DEVICE TYPENMOS "nch_lvt_5p0v" SOURCE LAYOUT
LVS DEVICE TYPENMOS "nch_svt_iso_5p0v" SOURCE LAYOUT
LVS DEVICE TYPENMOS "nch_ee_5p0v_pgm" SOURCE LAYOUT
LVS DEVICE TYPENMOS "nch_ee_5p0v_to_pgm" SOURCE LAYOUT
LVS DEVICE TYPENMOS "nch_ee_dp_5p0v_pgm" SOURCE LAYOUT
LVS DEVICE TYPENMOS "nch_dvt_5p0v" SOURCE LAYOUT
LVS DEVICE TYPENMOS "nch_dvt_iso_5p0v" SOURCE LAYOUT
LVS DEVICE TYPELDDNMOS "nch_dea_7v" SOURCE LAYOUT
LVS DEVICE TYPELDDNMOS "nch_dea_iso_7v" SOURCE LAYOUT
LVS DEVICE TYPELDDNMOS "nch_dea_12v" SOURCE LAYOUT
LVS DEVICE TYPELDDNMOS "nch_dea_20v" SOURCE LAYOUT
LVS DEVICE TYPELDDNMOS "nch_dea_24v" SOURCE LAYOUT
LVS DEVICE TYPELDDNMOS "nch_dea_30v" SOURCE LAYOUT
LVS DEVICE TYPELDDNMOS "nch_io_5p0v_4t" SOURCE LAYOUT
LVS DEVICE TYPELDDNMOS "nch_pp_5p0v_4t" SOURCE LAYOUT
LVS DEVICE TYPELDDNMOS "nch_io_iso_5p0v_6t" SOURCE LAYOUT
LVS DEVICE TYPELDDNMOS "nch_pp_iso_5p0v_6t" SOURCE LAYOUT
LVS DEVICE TYPELDDNMOS "nch_dea_dvt_24v" SOURCE LAYOUT
LVS DEVICE TYPEPMOS "pch_svt_5p0v" SOURCE LAYOUT
LVS DEVICE TYPEPMOS "pch_svt_iso_5p0v" SOURCE LAYOUT
LVS DEVICE TYPEPMOS "pch_des_ftr_20v" SOURCE LAYOUT
LVS DEVICE TYPELDDPMOS "pch_dea_7v" SOURCE LAYOUT
LVS DEVICE TYPELDDPMOS "pch_dea_12v" SOURCE LAYOUT
LVS DEVICE TYPELDDPMOS "pch_dea_20v" SOURCE LAYOUT
LVS DEVICE TYPELDDPMOS "pch_dea_24v" SOURCE LAYOUT
LVS DEVICE TYPELDDPMOS "pch_dea_30v" SOURCE LAYOUT
LVS DEVICE TYPELDDPMOS "pch_io_5p0v_5t" SOURCE LAYOUT
LVS DEVICE TYPELDDPMOS "pch_io_iso_5p0v_5t" SOURCE LAYOUT
LVS DEVICE TYPELDDPMOS "esd_hv_12v_prim" SOURCE LAYOUT
LVS DEVICE TYPELDDPMOS "esd_hv_24v_prim" SOURCE LAYOUT
LVS DEVICE TYPEDIODE "dio_stk_24v" SOURCE LAYOUT
LVS DEVICE TYPEDIODE "dio_stk_30v" SOURCE LAYOUT
LVS DEVICE TYPEDIODE "nch_io_5p0v" [ POS=D NEG=GSB ]SOURCE LAYOUT
LVS DEVICE TYPEDIODE "nch_pp_5p0v" [ POS=D NEG=GSB ]SOURCE LAYOUT
LVS DEVICE TYPEDIODE "pch_io_5p0v" [ POS=D NEG=GSB ]SOURCE LAYOUT
LVS DEVICE TYPEDIODE "esd_hv_pig_7v" [ POS=D NEG=GSB ]SOURCE LAYOUT
LVS DEVICE TYPEDIODE "esd_hv_iso_pig_7v" [ POS=D NEG=GSB ]SOURCE LAYOUT
// Reduction
LVS REDUCE SERIES MOSNO
LVS REDUCE PARALLEL MOSYES [ TOLERANCE length 0 ]
LVS REDUCE SEMI SERIES MOSNO
LVS REDUCE SPLIT GATESNO
LVS REDUCE PARALLEL BIPOLARYES
LVS REDUCE SERIES CAPACITORSNO
LVS REDUCE PARALLEL CAPACITORSYES
LVS REDUCE SERIES RESISTORSYES
LVS REDUCE PARALLEL RESISTORSNO
LVS REDUCE PARALLEL DIODESYES
LVS REDUCEdio_stk_24vPARALLEL [ TOLERANCE width 0 ]
LVS REDUCEdio_stk_30vPARALLEL [ TOLERANCE width 0 ]
LVS REDUCEpch_eprom_5p0v_pgmPARALLEL [ TOLERANCE length 0 option_vop 0 ]
LVS REDUCEnch_svt_iso_5p0vPARALLEL [ TOLERANCE length 0 option_vop 0 ]
LVS REDUCEpch_svt_iso_5p0vPARALLEL [ TOLERANCE length 0 option_vop 0 ]
LVS REDUCEpch_dea_7vPARALLEL [ TOLERANCE length 0 option_vop 0 ]
LVS REDUCEnch_dea_iso_7vPARALLEL [ TOLERANCE length 0 option_vop 0 ]
LVS REDUCEpch_dea_12vPARALLEL [ TOLERANCE length 0 option_vop 0 ]
LVS REDUCEpch_dea_20vPARALLEL [ TOLERANCE length 0 option_vop 0 ]
LVS REDUCEnch_ee_5p0v_to_pgmPARALLEL [ TOLERANCE length 0 option_vop 0 ]
LVS REDUCEnch_ee_dp_5p0v_pgmPARALLEL [ TOLERANCE length 0 option_vop 0 ]
LVS REDUCEnch_io_iso_5p0v_6tPARALLEL [ TOLERANCE length 0 option_vop 0 ]
LVS REDUCEnch_pp_iso_5p0v_6tPARALLEL [ TOLERANCE length 0 option_vop 0 ]
LVS REDUCEpch_io_iso_5p0v_5tPARALLEL [ TOLERANCE length 0 option_vop 0 ]
LVS REDUCEnch_dvt_iso_5p0vPARALLEL [ TOLERANCE length 0 option_vop 0 ]
LVS REDUCEesd_hv_iso_pig_7vPARALLEL [ TOLERANCE length 0 option_vop 0 ]
LVS REDUCEnch_io_5p0vPARALLEL [ TOLERANCE length 0 ]
LVS REDUCEpch_io_5p0vPARALLEL [ TOLERANCE length 0 ]
LVS REDUCEnch_pp_5p0vPARALLEL [ TOLERANCE length 0 ]
LVS REDUCEesd_hv_pig_7vPARALLEL [ TOLERANCE length 0 ]
LVS REDUCEesd_hv_12v_primPARALLEL [ TOLERANCE length 0 ]
LVS REDUCEesd_hv_24v_primPARALLEL [ TOLERANCE length 0 ]
LVS REDUCED(dio_z_mv)PARALLEL [ TOLERANCE option_vop 0 ]
LVS REDUCTION PRIORITYPARALLEL
// Filter
LVS FILTERRR == 0 SHORT SOURCE
// Trace Property
TRACE PROPERTYdinstpar(a) a 2
TRACE PROPERTYrinstpar(r) r 2
TRACE PROPERTYcinstpar(c) c 2
TRACE PROPERTYd(dio_z_mv)option_vop option_vop 0
TRACE PROPERTYd(dio_z_mv)instpar(a) a 2
TRACE PROPERTYdio_stk_30vwidth width 0
TRACE PROPERTYdio_stk_30vlength length 0
TRACE PROPERTYdio_stk_24vwidth width 0
TRACE PROPERTYdio_stk_24vlength length 0
TRACE PROPERTYpch_eprom_5p0v_pgmwidth width 0
TRACE PROPERTYpch_eprom_5p0v_pgmlength length 0
TRACE PROPERTYpch_eprom_5p0v_pgmoption_vop option_vop 0
TRACE PROPERTYnch_svt_5p0vwidth width 0
TRACE PROPERTYnch_svt_5p0vlength length 0
TRACE PROPERTYpch_svt_5p0vwidth width 0
TRACE PROPERTYpch_svt_5p0vlength length 0
TRACE PROPERTYnch_lvt_5p0vwidth width 0
TRACE PROPERTYnch_lvt_5p0vlength length 0
TRACE PROPERTYnch_svt_iso_5p0vwidth width 0
TRACE PROPERTYnch_svt_iso_5p0vlength length 0
TRACE PROPERTYpch_svt_iso_5p0vwidth width 0
TRACE PROPERTYpch_svt_iso_5p0vlength length 0
TRACE PROPERTYnch_dea_7vwidth width 0
TRACE PROPERTYnch_dea_7vlength length 0
TRACE PROPERTYpch_dea_7vwidth width 0
TRACE PROPERTYpch_dea_7vlength length 0
TRACE PROPERTYnch_dea_iso_7vwidth width 0
TRACE PROPERTYnch_dea_iso_7vlength length 0
TRACE PROPERTYnch_dea_12vwidth width 0
TRACE PROPERTYnch_dea_12vlength length 0
TRACE PROPERTYpch_dea_12vwidth width 0
TRACE PROPERTYpch_dea_12vlength length 0
TRACE PROPERTYnch_dea_20vwidth width 0
TRACE PROPERTYnch_dea_20vlength length 0
TRACE PROPERTYpch_dea_20vwidth width 0
TRACE PROPERTYpch_dea_20vlength length 0
TRACE PROPERTYnch_dea_24vwidth width 0
TRACE PROPERTYnch_dea_24vlength length 0
TRACE PROPERTYpch_dea_24vwidth width 0
TRACE PROPERTYpch_dea_24vlength length 0
TRACE PROPERTYnch_dea_30vwidth width 0
TRACE PROPERTYnch_dea_30vlength length 0
TRACE PROPERTYpch_dea_30vwidth width 0
TRACE PROPERTYpch_dea_30vlength length 0
TRACE PROPERTYpch_des_ftr_20vwidth width 0
TRACE PROPERTYpch_des_ftr_20vlength length 0
TRACE PROPERTYnch_io_5p0vwidth width 0
TRACE PROPERTYnch_io_5p0vlength length 0
TRACE PROPERTYpch_io_5p0vwidth width 0
TRACE PROPERTYpch_io_5p0vlength length 0
TRACE PROPERTYnch_pp_5p0vwidth width 0
TRACE PROPERTYnch_pp_5p0vlength length 0
TRACE PROPERTYnch_io_5p0v_4twidth width 0
TRACE PROPERTYnch_io_5p0v_4tlength length 0
TRACE PROPERTYpch_io_5p0v_5twidth width 0
TRACE PROPERTYpch_io_5p0v_5tlength length 0
TRACE PROPERTYnch_pp_5p0v_4twidth width 0
TRACE PROPERTYnch_pp_5p0v_4tlength length 0
TRACE PROPERTYnch_ee_5p0v_pgmwidth width 0
TRACE PROPERTYnch_ee_5p0v_pgmlength length 0
TRACE PROPERTYnch_ee_5p0v_to_pgmwidth width 0
TRACE PROPERTYnch_ee_5p0v_to_pgmlength length 0
TRACE PROPERTYnch_ee_dp_5p0v_pgmwidth width 0
TRACE PROPERTYnch_ee_dp_5p0v_pgmlength length 0
TRACE PROPERTYesd_hv_pig_7vwidth width 0
TRACE PROPERTYesd_hv_pig_7vlength length 0
TRACE PROPERTYesd_hv_12v_primwidth width 0
TRACE PROPERTYesd_hv_12v_primlength length 0
TRACE PROPERTYesd_hv_24v_primwidth width 0
TRACE PROPERTYesd_hv_24v_primlength length 0
TRACE PROPERTYnch_io_iso_5p0v_6twidth width 0
TRACE PROPERTYnch_io_iso_5p0v_6tlength length 0
TRACE PROPERTYnch_pp_iso_5p0v_6twidth width 0
TRACE PROPERTYnch_pp_iso_5p0v_6tlength length 0
TRACE PROPERTYpch_io_iso_5p0v_5twidth width 0
TRACE PROPERTYpch_io_iso_5p0v_5tlength length 0
TRACE PROPERTYnch_dvt_5p0vwidth width 0
TRACE PROPERTYnch_dvt_5p0vlength length 0
TRACE PROPERTYnch_dvt_iso_5p0vwidth width 0
TRACE PROPERTYnch_dvt_iso_5p0vlength length 0
TRACE PROPERTYnch_dea_dvt_24vwidth width 0
TRACE PROPERTYnch_dea_dvt_24vlength length 0
TRACE PROPERTYesd_hv_iso_pig_7vwidth width 0
TRACE PROPERTYesd_hv_iso_pig_7vlength length 0
TRACE PROPERTYnch_svt_iso_5p0voption_vop option_vop 0
TRACE PROPERTYpch_svt_iso_5p0voption_vop option_vop 0
TRACE PROPERTYnch_dea_iso_7voption_vop option_vop 0
TRACE PROPERTYpch_dea_7voption_vop option_vop 0
TRACE PROPERTYpch_dea_12voption_vop option_vop 0
TRACE PROPERTYpch_dea_20voption_vop option_vop 0
TRACE PROPERTYnch_ee_5p0v_to_pgmoption_vop option_vop 0
TRACE PROPERTYnch_ee_dp_5p0v_pgmoption_vop option_vop 0
TRACE PROPERTYnch_io_iso_5p0v_6toption_vop option_vop 0
TRACE PROPERTYnch_pp_iso_5p0v_6toption_vop option_vop 0
TRACE PROPERTYpch_io_iso_5p0v_5toption_vop option_vop 0
TRACE PROPERTYnch_dvt_iso_5p0voption_vop option_vop 0
TRACE PROPERTYesd_hv_iso_pig_7voption_vop option_vop 0
TRACE PROPERTYq(npn_v_8v_1x1)ea ea 0
TRACE PROPERTYq(npn_v_8v_2x2)ea ea 0
TRACE PROPERTYq(npn_v_8v_4x4)ea ea 0
TRACE PROPERTYq(npn_v_8v_8x8)ea ea 0
TRACE PROPERTYq(npn_v_8v_16x16)ea ea 0
TRACE PROPERTYq(pnp_s_20v_1x1)ea ea 0
TRACE PROPERTYq(pnp_s_20v_2x2)ea ea 0
TRACE PROPERTYq(pnp_s_20v_4x4)ea ea 0
TRACE PROPERTYq(pnp_s_20v_8x8)ea ea 0
TRACE PROPERTYq(pnp_s_20v_16x16)ea ea 0
TRACE PROPERTYq(npn_v_hv_5v_1x1)ea ea 0
TRACE PROPERTYq(npn_v_hv_5v_2x2)ea ea 0
TRACE PROPERTYq(npn_v_hv_5v_4x4)ea ea 0
TRACE PROPERTYq(npn_v_hv_5v_8x8)ea ea 0
TRACE PROPERTYq(npn_v_hv_5v_16x16)ea ea 0
TRACE PROPERTYq(pnp_v_hv_5v_1x1)ea ea 0
TRACE PROPERTYq(pnp_v_hv_5v_2x2)ea ea 0
TRACE PROPERTYq(pnp_v_hv_5v_4x4)ea ea 0
TRACE PROPERTYq(pnp_v_hv_5v_8x8)ea ea 0
TRACE PROPERTYq(pnp_v_hv_5v_16x16)ea ea 0

CELL COMPARISON RESULTS ( TOP LEVEL )

##########################
# ###
##NOT COMPARED#
# ###
##########################

Error:Different numbers of ports (see below).
Error:Power net missing in layout.
LAYOUT CELL NAME:2
SOURCE CELL NAME:2
--------------------------------------------------------------------------------------------------------------
INITIAL NUMBERS OF OBJECTS
--------------------------
LayoutSourceComponent Type
--------------------------
Ports:07*
Nets:710*
Instances:55nch_svt_5p0v (4 pins)
55pch_svt_5p0v (5 pins)
------------
Total Inst:1010

NUMBERS OF OBJECTS AFTER TRANSFORMATION
---------------------------------------
LayoutSourceComponent Type
--------------------------
Ports:07*
Nets:78*
Instances:45*nch_svt_5p0v (4 pins)
41*pch_svt_5p0v (5 pins)
02*SUP2 (3 pins)
------------
Total Inst:88

* = Number of objects in layout different from number in source.

**************************************************************************************************************
INFORMATION AND WARNINGS
**************************************************************************************************************

o Statistics:
4 layout mos transistors were reduced to 2.
2 mos transistors were deleted by parallel reduction.

**************************************************************************************************************
SUMMARY
**************************************************************************************************************
Total CPU Time:0 sec
Total Elapsed Time:0 sec

版图跟电路图的pin脚个数不对应，修改下cdl

check 一下merge的 gds ，ms 没有PG的mark

电源pin 没有，gds里面