set_zero_interconnect_delay_mode 如何理解
时间：10-02
整理：3721RD
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ICC的data_setUp阶段这三句话是要干嘛啊
set_zero_interconnect_delay_mode true
redirect -tee zic.timing { report_timing }
set_zero_interconnect_delay_mode false
，下面是set_zero_interconnect_delay_mode 描述，谁来解释一下啊
This command enables or disables the zero interconnect delay mode.The
zerointerconnectdelay mode forces the timer to ignore contributions
on a timing path from any wire capacitance in a design.It forcesall
wirecapacitancetobeas trivial as 0, regardless of the wire load
model used in the design or any back-annotated capacitance onawire.
Disabling the mode allows the timer to consider the wire capacitance as
it did before enabling the mode.
The command is used primarily in preplacement andpostplacementsteps
to assess design and constraint feasibility.When the mode is enabled,
the design is analyzed with only cell delay and the capacitance ofthe
pin load on all wires in the design to determine if the design can meet
timing goals.It also helps when debuggingpotentialmissingtiming
exceptionsinthe constraints.Zero interconnect delay mode must not
be used in the final implementation step.
set_zero_interconnect_delay_mode true
redirect -tee zic.timing { report_timing }
set_zero_interconnect_delay_mode false
，下面是set_zero_interconnect_delay_mode 描述，谁来解释一下啊
This command enables or disables the zero interconnect delay mode.The
zerointerconnectdelay mode forces the timer to ignore contributions
on a timing path from any wire capacitance in a design.It forcesall
wirecapacitancetobeas trivial as 0, regardless of the wire load
model used in the design or any back-annotated capacitance onawire.
Disabling the mode allows the timer to consider the wire capacitance as
it did before enabling the mode.
The command is used primarily in preplacement andpostplacementsteps
to assess design and constraint feasibility.When the mode is enabled,
the design is analyzed with only cell delay and the capacitance ofthe
pin load on all wires in the design to determine if the design can meet
timing goals.It also helps when debuggingpotentialmissingtiming
exceptionsinthe constraints.Zero interconnect delay mode must not
be used in the final implementation step.
這應該是一拿到netlist跟sdc後就要run
將net delay視為0(ideal)來看看timing有沒有meet constraint
如果在這個stage就看到很大的violation , 就要確認是那些violation , 可不可以waive或是false path等
check過後記得要設回false
跟楼上学习了，问问在什么情况下，我们可以设置线负载延时为0?