急求一篇solvnet上的文章，关于hvt lvt filler的？
https://solvnet.synopsys.com/retrieve/025405.html
邮箱：sallad@126.com
我还有个疑问，对于这种插filler的要求，在什么地方有说明吗?比如在某些rule或reference里有，我想了解一下这么做的原因是什么?
Question:
During the chip-finishing stage, how do I control the filler cells that are
placed between high threshold and standard threshold standard cell regions?
Answer:
IC Compiler supports voltage-threshold-aware filler cell insertion. The following flow
shows how to control the filler cells inserted between the standard threshold and
high threshold standard cells.
1. First, define a voltage threshold type for each of the voltage thresholds in
your design.
set_cell_vt_type -library ./libs/cmos10lphvt -vt_type vtType0
set_cell_vt_type -library ./libs/cmos10lplvt -vt_type vtType1
2. For each of the voltage threshold standard cell combinations, define the
voltage threshold rule for the filler cell to be inserted between those standard
cells as shown in the following example:
set_vt_filler_rule -threshold_voltage "vtType0 vtType1" \
-lib_cell "STH_FILL64 STH_FILL32 STH_FILL16 STH_FILL8 STH_FILL4 STH_FILL2 STH_FILL1")"
# use HT fillers between ST & HT cells
set_vt_filler_rule -threshold_voltage "vtType0 vtType0" \
-lib_cell "STH_FILL64 STH_FILL32 STH_FILL16 STH_FILL8 STH_FILL4 STH_FILL2 STH_FILL1"
# use HT fillers between HT & HT cells
set_vt_filler_rule -threshold_voltage "vtType1 vtType1" \
-lib_cell "STN_FILL64 STN_FILL32 STN_FIL
L16 STN_FILL8 STN_FILL4 STN_FILL2 STN_FILL1"
# use ST fillers between ST & ST Std cells
3. Run the insert_stdcell_filler command, which is voltage-threshold-aware, and insert
the filler cells according to the rules that you defined.
insert_stdcell_filler -respect_overlap -connect_to_power VDD -connect_to_ground VSS
Voltage-Threshold-Aware Filler Cell InsertionDoc Id: 025405Product: IC Compiler Last Modified: 01/07/2009
Question: During the chip-finishing stage, how do I control the filler cells that are placed between high threshold and standard threshold standard cell regions?Answer: IC Compiler supports voltage-threshold-aware filler cell insertion. The following flowshows how to control the filler cells inserted between the standard threshold and high threshold standard cells.1. First, define a voltage threshold type for each of the voltage thresholds inyour design. set_cell_vt_type -library ./libs/cmos10lphvt -vt_type vtType0set_cell_vt_type -library ./libs/cmos10lplvt -vt_type vtType12. For each of the voltage threshold standard cell combinations, define the voltage threshold rule for the filler cell to be inserted between those standardcells as shown in the following example:set_vt_filler_rule -threshold_voltage "vtType0 vtType1" \-lib_cell "STH_FILL64 STH_FILL32 STH_FILL16 STH_FILL8 STH_FILL4 STH_FILL2 STH_FILL1")"# use HT fillers between ST & HT cellsset_vt_filler_rule -threshold_voltage "vtType0 vtType0" \-lib_cell "STH_FILL64 STH_FILL32 STH_FILL16 STH_FILL8 STH_FILL4 STH_FILL2 STH_FILL1"# use HT fillers between HT & HT cellsset_vt_filler_rule -threshold_voltage "vtType1 vtType1" \-lib_cell "STN_FILL64 STN_FILL32 STN_FILL16 STN_FILL8 STN_FILL4 STN_FILL2 STN_FILL1"# use ST fillers between ST & ST Std cells3. Run the insert_stdcell_filler command, which is voltage-threshold-aware, and insert the filler cells according to the rules that you defined.insert_stdcell_filler -respect_overlap -connect_to_power VDD -connect_to_ground VSS
主要是一些老工艺的vth min width 要求决定的，比如min width为0.3um，而一个fill1h 的宽度为0.24 ，
则要靠近一个普通hvt cell才行的，.13um的老rule就是这样的，因此插入filler要写rule，比较累，
小尺寸工艺的min vth width要求比较小，一个filler1或2 就能满足，因此这种问题就没了，
谢谢各位的回答！现在明白了。
最近在看这个问题，看到你的回答，有点疑虑。如果是因为hvt的1x filler太窄才必须挨着一个hvt std cell的话，为啥不直接用一个rvt的1x filler呢，这样也不会违反你说到hvt min width要求呀，毕竟旁边的hvt std cell肯定是满足那个要求的（std cell最少好像都是2x宽度的吧）
现在这种问题少了，估计你碰不到， 65nm下几乎都不需要这个rule的
恩，是的。45以下都基本不用1x，28以下都没有1x filler了。