后端面试--每日一题（050） （已更正）

纪念每日一题累计到50，发一组选择题，从其中选一个最适合的答案，问题太多，不附带中文了
大致的难度在1和2之间

• 1) Chip utilization depends on ___.

a. Only on standard cells
b. Standard cells and macros
c. Only on macros
d. Standard cells macros and IO pads

• 2) In Soft blockages ____ cells are placed.

a. Only sequential cells
b. No cells
c. Only Buffers and Inverters
d. Any cells

• 3) Why we have to remove scan chains before placement?

a. Because scan chains are group of flip flop
b. It does not have timing critical path
c. It is series of flip flop connected in FIFO
d. None

• 4) Delay between shortest path and longest path in the clock is called ____.

a. Useful skew
b. Local skew
c. Global skew
d. Slack

• 5) Cross talk can be avoided by ___.

a. Decreasing the spacing between the metal layers
b. Shielding the nets
c.Using lower metal layers
d. Using long nets

• 6) Prerouting means routing of _____.

a. Clock nets
b. Signal nets
c. IO nets
d. the net with special requirement

• 7) Which of the following metal layer has Maximum resistance?

a. Metal1
b. Metal2
c. Metal3
d. Metal4

• 8) What is the major goal of CTS?

a. Minimum IR Drop
b. Minimum EM
c. Minimum Skew
d. Minimum Slack

• 9) Usually Hold is fixed ___.

a. Before Placement
b. After Placement
c. Before CTS
d. After CTS

• 10) To achieve better timing ____ cells are placed in the critical path.

a. HVT
b. LVT
c. RVT
d. SVT

• 11) Leakage power is inversely proportional to ___.

a. Frequency
b. Load Capacitance
c. Supply voltage
d. Threshold Voltage

• 12) Regular filler cells are added ___.

a. Before Placement of std cells
b. After Placement of Std Cells
c. Before Floor planning
d. Before Detail Routing

• 13) Search and Repair is used for ___.

a. Reducing IR Drop
b. Reducing DRC
c. Reducing EM violations
d. None

• 14) Maximum current density of a metal is available in ___.

a. .lib
b. .v
c. .tf
d. .sdc

• 15) More IR drop is due to ___.

a. Increase in metal width
b. Increase in metal length
c. Decrease in metal length
d. Lot of metal layers

• 16) The minimum height and width a cell can occupy in the design is called as ___.

a. Unit Tile cell
b. Multi heighten cell
c. LVT cell
d. HVT cell

• 17) CRPR stands for ___.

a. Cell Convergence Pessimism Removal
b. Cell Convergence Preset Removal
c. Clock Convergence Pessimism Removal
d. Clock Convergence Preset Removal

• 18) In OCV timing check, for setup time, ___.

a. Max delay is used for launch path and Min delay for capture path
b. Min delay is used for launch path and Max delay for capture path
c. BothMax delay is used for launch and Capture path
d. Both Min delay is used for both Capture and Launch paths

• 19) "Total metal area and(or) perimeter of conducting layer / gate to gate area"is called ___.

a. Utilization
b. Aspect Ratio
c. OCV
d. Antenna Ratio

• 20) The Solution for Antenna effect is ___.

a. Diode insertion
b. Shielding
c. Buffer insertion
d. Double spacing

• 21) To avoid cross talk, the shielded net is usually connected to ___.

a. floating
b. VSS
c. Both VDD and VSS
d. Clock

• 22) If the data is faster than the clock in Reg to Reg path ___ violation may come.

a. Setup
b. Hold
c. Both
d. None

• 23) (重复，删除)

• 24) Whichof the following is not present in SDC ___?

a. Max tran
b. Max cap
c. Max fanout
d. Max current density

• 25) Timing sanity check means (with respect to PD)___.

a. Checking timing of routed design with out net delays
b. CheckingTimingof placed design with net delays
c. Checking Timing of unplaced design without net delays
d. Checking Timing of routed design with net delays

• 26) Which of the following is having highest priority at final stage (post routed) of the design ___?

a. Setup violation
b. Hold violation
c. Skew
d. None

• 27) Which of the following is best suited for CTS?

a. CLKBUF and CLKINV
b. BUF
c. INV
d. all of them

• 28) In Wire bond chip, Max voltage dropwill be there at(with out macros) ___.

a. Left and Right sides
b. Bottom and Top sides
c. Middle
d. None

• 29) Which of the following is preferred while placing macros ___?

a. Macros placed center of the die
b. Macros placed left and right side of die
c. Macros placed bottom and top sides of die
d. Macros placed based on connectivity of the I/O

• 30) Routing congestion can be avoided by ___.

a. placing cells closer
b. Placing cells at corners
c. Distributing cells
d. None

• 31) Pitch of the wireis ___.

a. Min width
b. Min spacing
c. Min width - min spacing
d. Min width + min spacing

• 32) In Physical Design following step isnot there ___.

a. Floorplaning
b. Placement
c. Design Synthesis
d. CTS

• 33) In technology file if 7 metals are there then which metals you will use for power?

a. Metal1 and metal2
b. Metal3 and metal4
c. Metal5 and metal6
d. Metal6 and metal7

• 34) If metal6 and metal7 are used for the power in 7 metal layer process design then which metals you will use for clock ?

a. Metal1 and metal2
b. Metal3 and metal4
c. Metal4 and metal5
d. Metal6 and metal7

• 35) In a reg to reg timing path Tclocktoq delay is 0.5ns and TCombo delay is 5ns and Tsetup is 0.5ns then the clock period should be ___.

a. 1ns
b. 3ns
c. 5ns
d. 6ns

• 36) Difference between Clock buff/inverters and normal buff/inverters is __.

a. Clock buff/inverters are faster than normal buff/inverters
b. Clock buff/inverters are slower than normal buff/inverters
c. Clock buff/inverters are having equal rise and fall times with high drive strengths compare to normal buff/inverters
d. Normal buff/inverters are having equal rise and fall times with high drive strengths compare to Clock buff/inverters.

• 37) Which configuration is more preferred during floorplaning ?

a. Double back with flipped rows
b. Double back with non flipped rows
c. With channel spacing between rows and no double back
d. With channel spacing between rows and double back

• 38) What is the effect of high drive strength buffer when added in long net ?

a. Delay on the net increases
b. Capacitance on the net increases
c. Delay on the net decreases
d. Resistance on the net increases.

• 39) Delay of a cell depends on which factors ?

a. Output transition and input load
b. Input transition and Output load
c. Input transition and Output transition
d. Input load and Output Load.

• 40) After the final routing the violations in the design ___.

a. There can be no setup, no hold violations
b. There can be only setup violation but no hold
c. There can be only hold violation not Setup violation
d. There can be both violations.

• 41) Utilization of the chip after placement optimization will be ___.

a. Constant
b. Decrease
c. Increase
d. None of the above

• 42) What is routing congestion in the design?

a. Ratio of required routing tracks to available routing tracks
b. Ratio of available routing tracks to required routing tracks
c. Depends on the routing layers available
d. None of the above

我做完了，等着对答案，有一道不会，呵呵：
1-5：b c a c b
6-10:d a c d b
11-15: dd b c b
16-20: a c a d a
21-25: Xb d d c
26-30:a a c d c
31-35:dc d c d
36-40:c b c b c
41-44:c a a c

你不会的那题，问得不合理，我改过了，你再看下

21选c
而且。2楼的答案不知道是不是错乱了，似乎不太对啊，总共才42道还删了一个，，，，

2楼绝大部分是对的

晕呀 我看的时候是44道（加上重复的），那去掉一道，那不是全乱了哦

枪还没响你就跑了
幸好去掉的是最后2题
中间重复的题目，号继续保留着，问题被拿掉了
所以你的答案依然对得上号

哦，呵呵，这样子啊，期待标准答案啊，想看看哪个错了
21题还是不会，shielded net是什么，为什么要接0或者1呢，

我对strivenbu的这些答案有怀疑
1.3.4.12.40.
另外我不会37，我觉得a和b都可以啊，求解答

其实这组问题比较菜，不能细说，
我是用排除法，去掉最不合理的，留下什么算什么

表示压力阿

40选c?如果在final routing之后 还有hold violation 怎么修?

嘿嘿当成小测试了
期待正确答案打分打分

1-5, d c d c b
6-10, d a c d a
11-15, d a b c b
16-20, a a ad a
21-25, b b d c
26-30, b a c d c
31-35, d c d b d
36-40, c a c b b
41-42, c d
与2楼的有些差异。

01-05: d c b c b
06-10: d a c d b
11-15: d d b c b
16-20: a c a d a
21-25:b b x d c
26-30: b a c d c
31-35: d c d c d
36-40: c a c b d
41-42: c a

陈版， 错了7道， 算是啥水平啊！

因为有些问题不十分准确，而且涵盖的范围也不全面，并且没有明显的难易层次，不要太在意结果。
一般讲，应该在3～4分钟内完成，
错1～2题，可以算粗心
错3~4题，可能某个基本概念不清
错5~6题，新白领工人
错再多，好好努力吧

第21题我还是认为应该选c，VSS和VDD都可以起到屏蔽作用。
37题为什么b不可以?我觉得没什么分别啊
40题，设计的最后不应该有hold啊
请陈老大指点啊

#21：用得最多的是VSS(b)，而 c 的意思是同一条net，即加VSS又加VDD
#37：Double back 的意思就是 flipped rows，所以你做不出 Double back with non flipped rows
#40：这里的final route应该是detail route，不是final tapeout

学习了，
我属于努力中！

这个先收了 再说

第三题是不是应该选C更好呢?
（题目貌似是问为什么一定要，而不是问为什么可以）

你好啊，我想问下，chip utilization和core utilization有什么区别吗，core utilization是core的面积和chip的面积之比，那chip utilization是什么? 还有第12题中，add cell filler不是应该在post-route-opt之后加吗，因为add cell filler之后，利用率就100%，不能再进行opt了啊?多谢解答了