求助，如何理解并修正该时序报告中的错误
时间：10-02
整理：3721RD
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****************************************
Report : timing
-path full
-delay max
-max_paths 1
-sort_by group
Design : TOP
Version: C-2009.06-SP5
Date: Thu Aug 14 08:11:26 2014
****************************************
Operating Conditions: PwcV162T125_STD_CELL_7WLLibrary: PwcV162T125_STD_CELL_7WL
Wire Load Model Mode: enclosed
Startpoint: X2893_ZN (clock source 'X2893_ZN')
Endpoint: X5469_ZN (output port clocked by X2893_ZN)
Path Group: COMB
Path Type: max
Des/Clust/PortWire Load ModelLibrary
------------------------------------------------
TOP1KCELLS_4MZWBPwcV162T125_STD_CELL_7WL
PointIncrPath
--------------------------------------------------------------------------
clock X2893_ZN (fall edge)5.005.00
X2893_ZN (in)0.005.00 f
MI173/MI168/X6418/I_0/Z (INVERTBAL_H)0.055.05 r
MI173/MI168/X6417/C8/Z (AND2_F)0.155.20 r
MI173/MI168/X6417/I_0/Z (INVERTBAL_H)0.055.25 f
MI173/MI168/X6416/C8/Z (AND2_F)0.155.41 f
MI173/MI168/X6416/I_0/Z (INVERTBAL_H)0.055.46 r
MI173/MI168/X6415/C8/Z (AND2_F)0.165.61 r
MI173/MI168/X6415/I_0/Z (INVERTBAL_H)0.055.67 f
MI173/MI168/X6401/C8/Z (AND2_F)0.155.82 f
MI173/MI168/X6401/I_0/Z (INVERTBAL_H)0.055.87 r
MI173/MI168/X4998/C8/Z (AND2_F)0.166.03 r
MI173/MI168/X4998/I_0/Z (INVERTBAL_H)0.056.08 f
MI173/MI168/X6402/C8/Z (AND2_F)0.156.23 f
MI173/MI168/X6402/I_0/Z (INVERTBAL_H)0.056.28 r
MI173/MI168/X6409/C8/Z (AND2_F)0.166.44 r
MI173/MI168/X6409/I_0/Z (INVERTBAL_H)0.056.49 f
MI173/MI168/X6410/C8/Z (AND2_F)0.156.64 f
MI173/MI168/X6410/I_0/Z (INVERTBAL_H)0.056.69 r
MI173/MI168/X6404/C8/Z (AND2_F)0.166.85 r
MI173/MI168/X6404/I_0/Z (INVERTBAL_H)0.056.90 f
MI173/MI168/X6403/C8/Z (AND2_F)0.157.05 f
MI173/MI168/X6403/I_0/Z (INVERTBAL_H)0.057.11 r
MI173/MI168/X6406/C8/Z (AND2_F)0.167.26 r
MI173/MI168/X6406/I_0/Z (INVERTBAL_H)0.057.31 f
MI173/MI168/X6412/C8/Z (AND2_F)0.147.45 f
MI173/MI168/X6408/C8/Z (AND2_F)0.147.59 f
MI173/MI168/X6399/C8/Z (AND2_F)0.147.72 f
MI173/MI168/X6405/C8/Z (AND2_F)0.157.88 f
MI173/MI168/X6405/I_0/Z (INVERTBAL_H)0.067.93 r
MI173/MI168/X4817/C8/Z (OR2_I)0.148.08 r
MI173/MI168/X4817/I_0/Z (INVERTBAL_H)0.058.13 f
MI173/MI168/X6398/C8/Z (AND2_F)0.158.28 f
MI173/MI168/X6398/I_0/Z (INVERTBAL_H)0.058.33 r
MI173/MI168/X4242/C8/Z (AND2_F)2.8011.13 r
MI173/MI168/X4242/I_0/Z (INVERTBAL_H)0.4911.62 f
MI173/MI168/X5488/I_0/Z (INVERTBAL_H)0.0411.66 r
X5469_ZN (out)0.0011.66 r
data arrival time11.66
clock X2893_ZN (rise edge)10.0010.00
clock network delay (ideal)0.0010.00
clock uncertainty-1.009.00
output external delay-1.008.00
data required time8.00
--------------------------------------------------------------------------
data required time8.00
data arrival time-11.66
--------------------------------------------------------------------------
slack (VIOLATED)-3.66
Startpoint: MI24_Q5[3] (input port clocked by X2893_ZN)
Endpoint: MI173/MI93/X5322/Q_reg
(rising edge-triggered flip-flop clocked by X2893_ZN')
Path Group: INPUT
Path Type: max
Des/Clust/PortWire Load ModelLibrary
------------------------------------------------
TOP1KCELLS_4MZWBPwcV162T125_STD_CELL_7WL
PointIncrPath
-----------------------------------------------------------
clock X2893_ZN (rise edge)0.000.00
clock network delay (ideal)0.000.00
input external delay1.001.00 r
MI24_Q5[3] (in)0.201.20 r
U1397/Z (AND2_H)0.211.41 r
U415/Z (INVERT_F)0.101.51 f
U734/Z (NOR2_H)0.141.65 r
U1042/Z (NAND2_F)0.071.72 f
U635/Z (XNOR2_H)0.251.97 r
U1260/Z (NAND2BAL_H)0.092.06 f
U980/Z (AND2_I)0.162.22 f
U1088/Z (NAND2_F)0.102.31 r
U170/Z (AND2_I)0.182.50 r
U440/Z (NOR2_I)0.082.58 f
U1189/Z (NOR2_I)0.102.68 r
U303/Z (NAND2_B)0.162.84 f
U710/Z (AOI21_C)0.163.00 r
U707/Z (NOR2_D)0.103.10 f
U167/Z (XNOR2_C)0.213.31 f
U446/Z (XNOR2_F)0.283.59 r
U852/Z (NOR2_H)0.093.68 f
U284/Z (NAND2_H)0.103.77 r
U1133/Z (NAND2BAL_H)0.083.85 f
U1023/Z (NAND2_F)0.093.94 r
U1087/Z (NAND2_F)0.074.01 f
U977/Z (NAND2_F)0.104.12 r
U646/Z (NAND3_H)0.094.20 f
U1015/Z (NAND2BAL_H)0.094.29 r
U195/Z (AO22_J)0.174.46 r
U241/Z (AOI22_F)0.094.56 f
U258/Z (OAI21_F)0.134.68 r
U494/Z (NAND2_F)0.064.74 f
U893/Z (AND2_H)0.144.89 f
U761/Z (XOR3_H)0.215.10 r
U311/Z (XOR2_I)0.325.42 f
U308/Z (INVERT_I)0.095.51 r
U306/Z (NAND2_I)0.055.56 f
U307/Z (NAND2BAL_H)0.085.64 r
U194/Z (AOI22_C)0.105.75 f
U193/Z (AO22_H)0.215.96 f
U186/Z (AND2_I)0.156.11 f
U503/Z (OAI21_E)0.106.21 r
U746/Z (INVERT_F)0.046.25 f
MI173/MI93/X5322/Q_reg/D (DFFSR_E)0.006.25 f
data arrival time6.25
clock X2893_ZN' (rise edge)5.005.00
clock network delay (ideal)0.005.00
clock uncertainty-1.004.00
MI173/MI93/X5322/Q_reg/CLK (DFFSR_E)0.004.00 r
library setup time-0.133.87
data required time3.87
-----------------------------------------------------------
data required time3.87
data arrival time-6.25
-----------------------------------------------------------
slack (VIOLATED)-2.38
Startpoint: MI12/X129/Q_reg
(rising edge-triggered flip-flop clocked by X333_Z)
Endpoint: MI31_D[1] (output port clocked by X2893_ZN)
Path Group: OUTPUT
Path Type: max
Des/Clust/PortWire Load ModelLibrary
------------------------------------------------
TOP1KCELLS_4MZWBPwcV162T125_STD_CELL_7WL
PointIncrPath
-----------------------------------------------------------
clock X333_Z (rise edge)0.000.00
clock network delay (ideal)0.000.00
MI12/X129/Q_reg/CLK (DFFR_E)0.000.00 r
MI12/X129/Q_reg/Q (DFFR_E)0.450.45 r
MI12/X3847/C8/Z (AND2_F)0.160.61 r
MI12/X3847/I_0/Z (INVERTBAL_H)0.050.66 f
MI12/X5050/C8/Z (AND2_F)0.150.81 f
MI12/X5050/I_0/Z (INVERTBAL_H)0.050.86 r
MI31_D[1] (out)0.000.86 r
data arrival time0.86
clock X2893_ZN (rise edge)10.0010.00
clock network delay (ideal)0.0010.00
clock uncertainty-1.009.00
output external delay-1.008.00
data required time8.00
-----------------------------------------------------------
data required time8.00
data arrival time-0.86
-----------------------------------------------------------
slack (MET)7.14
Startpoint: MI12/X132/Q_reg
(rising edge-triggered flip-flop clocked by X350_Z)
Endpoint: MI64/X128/Q_reg
(rising edge-triggered flip-flop clocked by X333_Z)
Path Group: X333_Z
Path Type: max
Des/Clust/PortWire Load ModelLibrary
------------------------------------------------
TOP1KCELLS_4MZWBPwcV162T125_STD_CELL_7WL
PointIncrPath
-----------------------------------------------------------
clock X350_Z (rise edge)0.000.00
clock network delay (ideal)0.000.00
MI12/X132/Q_reg/CLK (DFFR_E)0.000.00 r
MI12/X132/Q_reg/Q (DFFR_E)0.480.48 r
U541/Z (AND2_H)0.160.64 r
MI12/X3039/I_0/Z (INVERTBAL_H)0.070.71 f
MI12/X5512/I_0/Z (INVERTBAL_H)0.060.77 r
U36/Z (XOR2_A)0.321.09 r
U38/Z (AO22_B)0.441.53 r
U33/Z (XOR2_A)0.361.88 r
U35/Z (AO22_B)0.542.42 r
U539/Z (XOR2_F)0.292.71 r
U538/Z (AO22_H)0.272.98 r
MI64/X3033/C8/Z (AND2_F)0.183.16 r
MI64/X3033/I_0/Z (INVERTBAL_H)0.053.21 f
MI64/X5072/C8/Z (AND2_F)0.153.35 f
MI64/X5072/I_0/Z (INVERTBAL_H)0.123.47 r
MI64/X3149/C8/Z (AND2_F)0.173.64 r
MI64/X3149/I_0/Z (INVERTBAL_H)0.053.70 f
MI64/X3151/C8/Z (AND2_F)0.153.84 f
MI64/X3151/I_0/Z (INVERTBAL_H)0.083.92 r
MI64/X3043/C8/Z (AND2_F)0.164.08 r
MI64/X3043/I_0/Z (INVERTBAL_H)0.054.13 f
MI64/X3962/C8/Z (AND2_F)0.154.28 f
MI64/X3962/I_0/Z (INVERTBAL_H)0.094.37 r
MI64/X3226/C8/Z (AND2_F)0.164.53 r
MI64/X3226/I_0/Z (INVERTBAL_H)0.054.58 f
MI64/X3702/C8/Z (AND2_F)0.154.73 f
MI64/X3702/I_0/Z (INVERTBAL_H)0.084.81 r
MI64/X724/I_1/Z (INVERTBAL_H)0.054.86 f
MI64/X724/C10/Z (AND2_F)0.145.00 f
MI64/X724/C7/Z (OR2_I)0.175.17 f
MI64/X128/Q_reg/D (DFFR_E)0.005.17 f
data arrival time5.17
clock X333_Z (rise edge)10.0010.00
clock network delay (ideal)0.0010.00
clock uncertainty-1.009.00
MI64/X128/Q_reg/CLK (DFFR_E)0.009.00 r
library setup time-0.328.68
data required time8.68
-----------------------------------------------------------
data required time8.68
data arrival time-5.17
-----------------------------------------------------------
slack (MET)3.51
Startpoint: MI173/MI94/X5311/Q_reg
(rising edge-triggered flip-flop clocked by X2893_ZN')
Endpoint: MI12/X69/Q_reg
(rising edge-triggered flip-flop clocked by X350_Z)
Path Group: X350_Z
Path Type: max
Des/Clust/PortWire Load ModelLibrary
------------------------------------------------
TOP1KCELLS_4MZWBPwcV162T125_STD_CELL_7WL
PointIncrPath
--------------------------------------------------------------------------
clock X2893_ZN' (rise edge)5.005.00
clock network delay (ideal)0.005.00
MI173/MI94/X5311/Q_reg/CLK (DFFSR_E)0.005.00 r
MI173/MI94/X5311/Q_reg/Q (DFFSR_E)0.385.38 r
MI12/X69/Q_reg/D (DFFR_E)0.005.38 r
data arrival time5.38
clock X350_Z (rise edge)10.0010.00
clock network delay (ideal)0.0010.00
clock uncertainty-1.009.00
MI12/X69/Q_reg/CLK (DFFR_E)0.009.00 r
library setup time-0.198.81
data required time8.81
--------------------------------------------------------------------------
data required time8.81
data arrival time-5.38
--------------------------------------------------------------------------
slack (MET)3.43
Startpoint: MI173/MI9/X6342/Q_reg
(rising edge-triggered flip-flop clocked by X2893_ZN')
Endpoint: MI173/MI93/X5322/Q_reg
(rising edge-triggered flip-flop clocked by X2893_ZN)
Path Group: X2893_ZN
Path Type: max
Des/Clust/PortWire Load ModelLibrary
------------------------------------------------
TOP1KCELLS_4MZWBPwcV162T125_STD_CELL_7WL
PointIncrPath
-----------------------------------------------------------
clock X2893_ZN' (rise edge)5.005.00
clock network delay (ideal)0.005.00
MI173/MI9/X6342/Q_reg/CLK (DFFR_E)0.005.00 r
MI173/MI9/X6342/Q_reg/QBAR (DFFR_E)0.295.29 f
U791/Z (INVERTBAL_E)0.105.39 r
U813/Z (AND2_H)0.155.54 r
U635/Z (XNOR2_H)0.215.75 f
U1260/Z (NAND2BAL_H)0.085.83 r
U980/Z (AND2_I)0.165.99 r
U1088/Z (NAND2_F)0.076.06 f
U170/Z (AND2_I)0.176.24 f
U440/Z (NOR2_I)0.096.33 r
U1189/Z (NOR2_I)0.096.42 f
U303/Z (NAND2_B)0.196.60 r
U710/Z (AOI21_C)0.156.75 f
U707/Z (NOR2_D)0.136.88 r
U167/Z (XNOR2_C)0.227.10 r
U446/Z (XNOR2_F)0.247.34 r
U852/Z (NOR2_H)0.097.43 f
U284/Z (NAND2_H)0.107.53 r
U1133/Z (NAND2BAL_H)0.087.61 f
U1023/Z (NAND2_F)0.097.70 r
U1087/Z (NAND2_F)0.077.77 f
U977/Z (NAND2_F)0.107.87 r
U646/Z (NAND3_H)0.097.96 f
U1015/Z (NAND2BAL_H)0.098.04 r
U195/Z (AO22_J)0.178.21 r
U241/Z (AOI22_F)0.098.31 f
U258/Z (OAI21_F)0.138.44 r
U494/Z (NAND2_F)0.068.50 f
U893/Z (AND2_H)0.148.64 f
U761/Z (XOR3_H)0.218.86 r
U311/Z (XOR2_I)0.329.17 f
U308/Z (INVERT_I)0.099.26 r
U306/Z (NAND2_I)0.059.32 f
U307/Z (NAND2BAL_H)0.089.40 r
U194/Z (AOI22_C)0.109.50 f
U193/Z (AO22_H)0.219.72 f
U186/Z (AND2_I)0.159.86 f
U503/Z (OAI21_E)0.109.97 r
U746/Z (INVERT_F)0.0410.00 f
MI173/MI93/X5322/Q_reg/D (DFFSR_E)0.0010.00 f
data arrival time10.00
clock X2893_ZN (rise edge)10.0010.00
clock network delay (ideal)0.0010.00
clock uncertainty-1.009.00
MI173/MI93/X5322/Q_reg/CLK (DFFSR_E)0.009.00 r
library setup time-0.138.87
data required time8.87
-----------------------------------------------------------
data required time8.87
data arrival time-10.00
-----------------------------------------------------------
slack (VIOLATED)-1.13
Report : timing
-path full
-delay max
-max_paths 1
-sort_by group
Design : TOP
Version: C-2009.06-SP5
Date: Thu Aug 14 08:11:26 2014
****************************************
Operating Conditions: PwcV162T125_STD_CELL_7WLLibrary: PwcV162T125_STD_CELL_7WL
Wire Load Model Mode: enclosed
Startpoint: X2893_ZN (clock source 'X2893_ZN')
Endpoint: X5469_ZN (output port clocked by X2893_ZN)
Path Group: COMB
Path Type: max
Des/Clust/PortWire Load ModelLibrary
------------------------------------------------
TOP1KCELLS_4MZWBPwcV162T125_STD_CELL_7WL
PointIncrPath
--------------------------------------------------------------------------
clock X2893_ZN (fall edge)5.005.00
X2893_ZN (in)0.005.00 f
MI173/MI168/X6418/I_0/Z (INVERTBAL_H)0.055.05 r
MI173/MI168/X6417/C8/Z (AND2_F)0.155.20 r
MI173/MI168/X6417/I_0/Z (INVERTBAL_H)0.055.25 f
MI173/MI168/X6416/C8/Z (AND2_F)0.155.41 f
MI173/MI168/X6416/I_0/Z (INVERTBAL_H)0.055.46 r
MI173/MI168/X6415/C8/Z (AND2_F)0.165.61 r
MI173/MI168/X6415/I_0/Z (INVERTBAL_H)0.055.67 f
MI173/MI168/X6401/C8/Z (AND2_F)0.155.82 f
MI173/MI168/X6401/I_0/Z (INVERTBAL_H)0.055.87 r
MI173/MI168/X4998/C8/Z (AND2_F)0.166.03 r
MI173/MI168/X4998/I_0/Z (INVERTBAL_H)0.056.08 f
MI173/MI168/X6402/C8/Z (AND2_F)0.156.23 f
MI173/MI168/X6402/I_0/Z (INVERTBAL_H)0.056.28 r
MI173/MI168/X6409/C8/Z (AND2_F)0.166.44 r
MI173/MI168/X6409/I_0/Z (INVERTBAL_H)0.056.49 f
MI173/MI168/X6410/C8/Z (AND2_F)0.156.64 f
MI173/MI168/X6410/I_0/Z (INVERTBAL_H)0.056.69 r
MI173/MI168/X6404/C8/Z (AND2_F)0.166.85 r
MI173/MI168/X6404/I_0/Z (INVERTBAL_H)0.056.90 f
MI173/MI168/X6403/C8/Z (AND2_F)0.157.05 f
MI173/MI168/X6403/I_0/Z (INVERTBAL_H)0.057.11 r
MI173/MI168/X6406/C8/Z (AND2_F)0.167.26 r
MI173/MI168/X6406/I_0/Z (INVERTBAL_H)0.057.31 f
MI173/MI168/X6412/C8/Z (AND2_F)0.147.45 f
MI173/MI168/X6408/C8/Z (AND2_F)0.147.59 f
MI173/MI168/X6399/C8/Z (AND2_F)0.147.72 f
MI173/MI168/X6405/C8/Z (AND2_F)0.157.88 f
MI173/MI168/X6405/I_0/Z (INVERTBAL_H)0.067.93 r
MI173/MI168/X4817/C8/Z (OR2_I)0.148.08 r
MI173/MI168/X4817/I_0/Z (INVERTBAL_H)0.058.13 f
MI173/MI168/X6398/C8/Z (AND2_F)0.158.28 f
MI173/MI168/X6398/I_0/Z (INVERTBAL_H)0.058.33 r
MI173/MI168/X4242/C8/Z (AND2_F)2.8011.13 r
MI173/MI168/X4242/I_0/Z (INVERTBAL_H)0.4911.62 f
MI173/MI168/X5488/I_0/Z (INVERTBAL_H)0.0411.66 r
X5469_ZN (out)0.0011.66 r
data arrival time11.66
clock X2893_ZN (rise edge)10.0010.00
clock network delay (ideal)0.0010.00
clock uncertainty-1.009.00
output external delay-1.008.00
data required time8.00
--------------------------------------------------------------------------
data required time8.00
data arrival time-11.66
--------------------------------------------------------------------------
slack (VIOLATED)-3.66
Startpoint: MI24_Q5[3] (input port clocked by X2893_ZN)
Endpoint: MI173/MI93/X5322/Q_reg
(rising edge-triggered flip-flop clocked by X2893_ZN')
Path Group: INPUT
Path Type: max
Des/Clust/PortWire Load ModelLibrary
------------------------------------------------
TOP1KCELLS_4MZWBPwcV162T125_STD_CELL_7WL
PointIncrPath
-----------------------------------------------------------
clock X2893_ZN (rise edge)0.000.00
clock network delay (ideal)0.000.00
input external delay1.001.00 r
MI24_Q5[3] (in)0.201.20 r
U1397/Z (AND2_H)0.211.41 r
U415/Z (INVERT_F)0.101.51 f
U734/Z (NOR2_H)0.141.65 r
U1042/Z (NAND2_F)0.071.72 f
U635/Z (XNOR2_H)0.251.97 r
U1260/Z (NAND2BAL_H)0.092.06 f
U980/Z (AND2_I)0.162.22 f
U1088/Z (NAND2_F)0.102.31 r
U170/Z (AND2_I)0.182.50 r
U440/Z (NOR2_I)0.082.58 f
U1189/Z (NOR2_I)0.102.68 r
U303/Z (NAND2_B)0.162.84 f
U710/Z (AOI21_C)0.163.00 r
U707/Z (NOR2_D)0.103.10 f
U167/Z (XNOR2_C)0.213.31 f
U446/Z (XNOR2_F)0.283.59 r
U852/Z (NOR2_H)0.093.68 f
U284/Z (NAND2_H)0.103.77 r
U1133/Z (NAND2BAL_H)0.083.85 f
U1023/Z (NAND2_F)0.093.94 r
U1087/Z (NAND2_F)0.074.01 f
U977/Z (NAND2_F)0.104.12 r
U646/Z (NAND3_H)0.094.20 f
U1015/Z (NAND2BAL_H)0.094.29 r
U195/Z (AO22_J)0.174.46 r
U241/Z (AOI22_F)0.094.56 f
U258/Z (OAI21_F)0.134.68 r
U494/Z (NAND2_F)0.064.74 f
U893/Z (AND2_H)0.144.89 f
U761/Z (XOR3_H)0.215.10 r
U311/Z (XOR2_I)0.325.42 f
U308/Z (INVERT_I)0.095.51 r
U306/Z (NAND2_I)0.055.56 f
U307/Z (NAND2BAL_H)0.085.64 r
U194/Z (AOI22_C)0.105.75 f
U193/Z (AO22_H)0.215.96 f
U186/Z (AND2_I)0.156.11 f
U503/Z (OAI21_E)0.106.21 r
U746/Z (INVERT_F)0.046.25 f
MI173/MI93/X5322/Q_reg/D (DFFSR_E)0.006.25 f
data arrival time6.25
clock X2893_ZN' (rise edge)5.005.00
clock network delay (ideal)0.005.00
clock uncertainty-1.004.00
MI173/MI93/X5322/Q_reg/CLK (DFFSR_E)0.004.00 r
library setup time-0.133.87
data required time3.87
-----------------------------------------------------------
data required time3.87
data arrival time-6.25
-----------------------------------------------------------
slack (VIOLATED)-2.38
Startpoint: MI12/X129/Q_reg
(rising edge-triggered flip-flop clocked by X333_Z)
Endpoint: MI31_D[1] (output port clocked by X2893_ZN)
Path Group: OUTPUT
Path Type: max
Des/Clust/PortWire Load ModelLibrary
------------------------------------------------
TOP1KCELLS_4MZWBPwcV162T125_STD_CELL_7WL
PointIncrPath
-----------------------------------------------------------
clock X333_Z (rise edge)0.000.00
clock network delay (ideal)0.000.00
MI12/X129/Q_reg/CLK (DFFR_E)0.000.00 r
MI12/X129/Q_reg/Q (DFFR_E)0.450.45 r
MI12/X3847/C8/Z (AND2_F)0.160.61 r
MI12/X3847/I_0/Z (INVERTBAL_H)0.050.66 f
MI12/X5050/C8/Z (AND2_F)0.150.81 f
MI12/X5050/I_0/Z (INVERTBAL_H)0.050.86 r
MI31_D[1] (out)0.000.86 r
data arrival time0.86
clock X2893_ZN (rise edge)10.0010.00
clock network delay (ideal)0.0010.00
clock uncertainty-1.009.00
output external delay-1.008.00
data required time8.00
-----------------------------------------------------------
data required time8.00
data arrival time-0.86
-----------------------------------------------------------
slack (MET)7.14
Startpoint: MI12/X132/Q_reg
(rising edge-triggered flip-flop clocked by X350_Z)
Endpoint: MI64/X128/Q_reg
(rising edge-triggered flip-flop clocked by X333_Z)
Path Group: X333_Z
Path Type: max
Des/Clust/PortWire Load ModelLibrary
------------------------------------------------
TOP1KCELLS_4MZWBPwcV162T125_STD_CELL_7WL
PointIncrPath
-----------------------------------------------------------
clock X350_Z (rise edge)0.000.00
clock network delay (ideal)0.000.00
MI12/X132/Q_reg/CLK (DFFR_E)0.000.00 r
MI12/X132/Q_reg/Q (DFFR_E)0.480.48 r
U541/Z (AND2_H)0.160.64 r
MI12/X3039/I_0/Z (INVERTBAL_H)0.070.71 f
MI12/X5512/I_0/Z (INVERTBAL_H)0.060.77 r
U36/Z (XOR2_A)0.321.09 r
U38/Z (AO22_B)0.441.53 r
U33/Z (XOR2_A)0.361.88 r
U35/Z (AO22_B)0.542.42 r
U539/Z (XOR2_F)0.292.71 r
U538/Z (AO22_H)0.272.98 r
MI64/X3033/C8/Z (AND2_F)0.183.16 r
MI64/X3033/I_0/Z (INVERTBAL_H)0.053.21 f
MI64/X5072/C8/Z (AND2_F)0.153.35 f
MI64/X5072/I_0/Z (INVERTBAL_H)0.123.47 r
MI64/X3149/C8/Z (AND2_F)0.173.64 r
MI64/X3149/I_0/Z (INVERTBAL_H)0.053.70 f
MI64/X3151/C8/Z (AND2_F)0.153.84 f
MI64/X3151/I_0/Z (INVERTBAL_H)0.083.92 r
MI64/X3043/C8/Z (AND2_F)0.164.08 r
MI64/X3043/I_0/Z (INVERTBAL_H)0.054.13 f
MI64/X3962/C8/Z (AND2_F)0.154.28 f
MI64/X3962/I_0/Z (INVERTBAL_H)0.094.37 r
MI64/X3226/C8/Z (AND2_F)0.164.53 r
MI64/X3226/I_0/Z (INVERTBAL_H)0.054.58 f
MI64/X3702/C8/Z (AND2_F)0.154.73 f
MI64/X3702/I_0/Z (INVERTBAL_H)0.084.81 r
MI64/X724/I_1/Z (INVERTBAL_H)0.054.86 f
MI64/X724/C10/Z (AND2_F)0.145.00 f
MI64/X724/C7/Z (OR2_I)0.175.17 f
MI64/X128/Q_reg/D (DFFR_E)0.005.17 f
data arrival time5.17
clock X333_Z (rise edge)10.0010.00
clock network delay (ideal)0.0010.00
clock uncertainty-1.009.00
MI64/X128/Q_reg/CLK (DFFR_E)0.009.00 r
library setup time-0.328.68
data required time8.68
-----------------------------------------------------------
data required time8.68
data arrival time-5.17
-----------------------------------------------------------
slack (MET)3.51
Startpoint: MI173/MI94/X5311/Q_reg
(rising edge-triggered flip-flop clocked by X2893_ZN')
Endpoint: MI12/X69/Q_reg
(rising edge-triggered flip-flop clocked by X350_Z)
Path Group: X350_Z
Path Type: max
Des/Clust/PortWire Load ModelLibrary
------------------------------------------------
TOP1KCELLS_4MZWBPwcV162T125_STD_CELL_7WL
PointIncrPath
--------------------------------------------------------------------------
clock X2893_ZN' (rise edge)5.005.00
clock network delay (ideal)0.005.00
MI173/MI94/X5311/Q_reg/CLK (DFFSR_E)0.005.00 r
MI173/MI94/X5311/Q_reg/Q (DFFSR_E)0.385.38 r
MI12/X69/Q_reg/D (DFFR_E)0.005.38 r
data arrival time5.38
clock X350_Z (rise edge)10.0010.00
clock network delay (ideal)0.0010.00
clock uncertainty-1.009.00
MI12/X69/Q_reg/CLK (DFFR_E)0.009.00 r
library setup time-0.198.81
data required time8.81
--------------------------------------------------------------------------
data required time8.81
data arrival time-5.38
--------------------------------------------------------------------------
slack (MET)3.43
Startpoint: MI173/MI9/X6342/Q_reg
(rising edge-triggered flip-flop clocked by X2893_ZN')
Endpoint: MI173/MI93/X5322/Q_reg
(rising edge-triggered flip-flop clocked by X2893_ZN)
Path Group: X2893_ZN
Path Type: max
Des/Clust/PortWire Load ModelLibrary
------------------------------------------------
TOP1KCELLS_4MZWBPwcV162T125_STD_CELL_7WL
PointIncrPath
-----------------------------------------------------------
clock X2893_ZN' (rise edge)5.005.00
clock network delay (ideal)0.005.00
MI173/MI9/X6342/Q_reg/CLK (DFFR_E)0.005.00 r
MI173/MI9/X6342/Q_reg/QBAR (DFFR_E)0.295.29 f
U791/Z (INVERTBAL_E)0.105.39 r
U813/Z (AND2_H)0.155.54 r
U635/Z (XNOR2_H)0.215.75 f
U1260/Z (NAND2BAL_H)0.085.83 r
U980/Z (AND2_I)0.165.99 r
U1088/Z (NAND2_F)0.076.06 f
U170/Z (AND2_I)0.176.24 f
U440/Z (NOR2_I)0.096.33 r
U1189/Z (NOR2_I)0.096.42 f
U303/Z (NAND2_B)0.196.60 r
U710/Z (AOI21_C)0.156.75 f
U707/Z (NOR2_D)0.136.88 r
U167/Z (XNOR2_C)0.227.10 r
U446/Z (XNOR2_F)0.247.34 r
U852/Z (NOR2_H)0.097.43 f
U284/Z (NAND2_H)0.107.53 r
U1133/Z (NAND2BAL_H)0.087.61 f
U1023/Z (NAND2_F)0.097.70 r
U1087/Z (NAND2_F)0.077.77 f
U977/Z (NAND2_F)0.107.87 r
U646/Z (NAND3_H)0.097.96 f
U1015/Z (NAND2BAL_H)0.098.04 r
U195/Z (AO22_J)0.178.21 r
U241/Z (AOI22_F)0.098.31 f
U258/Z (OAI21_F)0.138.44 r
U494/Z (NAND2_F)0.068.50 f
U893/Z (AND2_H)0.148.64 f
U761/Z (XOR3_H)0.218.86 r
U311/Z (XOR2_I)0.329.17 f
U308/Z (INVERT_I)0.099.26 r
U306/Z (NAND2_I)0.059.32 f
U307/Z (NAND2BAL_H)0.089.40 r
U194/Z (AOI22_C)0.109.50 f
U193/Z (AO22_H)0.219.72 f
U186/Z (AND2_I)0.159.86 f
U503/Z (OAI21_E)0.109.97 r
U746/Z (INVERT_F)0.0410.00 f
MI173/MI93/X5322/Q_reg/D (DFFSR_E)0.0010.00 f
data arrival time10.00
clock X2893_ZN (rise edge)10.0010.00
clock network delay (ideal)0.0010.00
clock uncertainty-1.009.00
MI173/MI93/X5322/Q_reg/CLK (DFFSR_E)0.009.00 r
library setup time-0.138.87
data required time8.87
-----------------------------------------------------------
data required time8.87
data arrival time-10.00
-----------------------------------------------------------
slack (VIOLATED)-1.13
满满的贴了一堆报告，下面对电路做一个简单介绍
有三个Clock:X2893_ZN X350_Z X333_Z,三者虽然同频同相，但是在电路外面经过了不同的门控，所以在这里只能分开用。请问如何create_clock?
从X2893_ZN到 X5469_ZN有一条直接通路，属于COMB路径组的，为什么COMB时序报告中X2893_ZN是从半周期开始算起?
为什么Input路径组的required timing也是从half_cycle开始计算的?
CLK->Q的延迟为0.45，算是很大吗?Q后面只连接一个AND2门啊
第1个是用与门或门做的门控时钟吗，没有电路，不太清楚
第2个和最后1个都是一个沿打出数据，另一个沿采，确定是设计的本意?若是的话，要么让工具拼命优化了，但这么大的slack，估计也优化不了，要么看约束能否放松一些，要么前端修改下设计，要么PR时调整时钟相位去满足这条路径了。
没有注意到时钟后面括号里的fall edge吗
还有，clock XXX' 时钟名XXX右上角的’
先看第一个吧，这组路径叫做COMB，是从INPUT到OUTPUT的组合路径，这个从2893到5469就是经过与非门的门控时钟电路，求解为什么路径起始点是从2893的半周期出开始计算的呢?
仔细看了下，这条路径确不属于门控时钟。
情况是不是这样的：
时钟2893经过一系列组合逻辑，输出到端口上。同时对该端口约束了output delay，且关联时钟是2893?
如果是这样，就不该施加output delay的约束。因为2893被定义为时钟，经过一系列的与或门和inv，最终仍然是一个时钟，没有道理对一个时钟端口设置output delay
但既然设了，工具只能这样分析，即从输入信号相当于2893时钟正沿之前最近的一次变化开始计算。同时应该会报一些关于时钟关联到了数据路径的警告吧
如果情况不是这样的，再讨论
确实如你所说，我对5469这个OUTPUT添加了output_delay的约束。
去掉该约束之后应该就会把这条路径当做门控来处理了吧?
我试了试去除5469上的OUTPUT_DELAY约束，发现时序变好了，没有了刚才的时序违例，而且面积减小了很多
还没写完就发了，现在还有两个问题没有理解：
一个是我的三个时钟是外部从一个时钟源经过门控之后给到我的设计，请问这三个时钟是采用三个create_clock好呢，还是用一个create_clock和两个create_generated好呢，我觉得是第一个，但有同学说是第二个，你怎么看?
第二个是综合的时候出现HOLD违例和TRANSITION、MAX_CAP 违例，但是综合的时候不知道怎么修复，而且到了后端PR，发现TRANSITIO、MAX_CAP违例越发严重，老兄你对set_max_transition和set_max_capacitance有什么好的意见吗，出现违例应该怎么修复呢?
1，要看这三个时钟域之间是否存在路径，若不存在，是可以都用create clock声明的。但若存在路径，就要用create generate clock声明，以便时序分析工具能计算出这些时钟的相位差。
2，综合时的hold违例是可以不关注的。max transition和max cap在综合阶段fix掉也没有多大意义，留给pr处理吧。这两个的约束值应该参考lib，max transition如果lib中有说明的话，可以不设，没有就参照lib中时序查找表的transition坐标的上限，略小一点就可以。lib中各个cell的输出pin的max cap不尽相同，不必约束它。我不清楚pr修复时为什么会越发严重，一般pr对setup/hold和drc反复修复一下就应该差不多了。需要注意的是，综合时不要修复时钟和复位的transition/cap问题，一般它们的负载都比较大，设置ideal network即可，pr处理的效果会更好
谢谢你的解答，我已经搞定这个问题了