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求大神帮忙看看,为什么我综合完 cell delay都是0?新手求助

时间:10-02 整理:3721RD 点击:
综合后发现cell delay都是零,很奇怪:
1、
****************************************
Report : timing
-path full_clock
-delay max
-nworst 10
-max_paths 10
Design : multiplier
Version: B-2008.09
Date: Mon May 19 20:47:02 2014
****************************************
Operating Conditions: NCCOMLibrary: tpz973gtc
Wire Load Model Mode: top
Startpoint: dataout_reg[0]
(rising edge-triggered flip-flop clocked by clk)
Endpoint: dataout[0] (output port clocked by clk)
Path Group: clk
Path Type: max
Des/Clust/PortWire Load ModelLibrary
------------------------------------------------
multiplierTSMC128K_Conservative tpz973gtc
PointIncrPath
-----------------------------------------------------------
clock clk (rise edge)0.000.00
clock network delay (ideal)0.200.20
dataout_reg[0]/CK (DFFTRX1)0.000.20 r
dataout_reg[0]/Q (DFFTRX1)0.000.20 r
6/Y (CLKBUFX8)0.000.20 r
dataout[0] (out)0.000.20 r
data arrival time0.20
clock clk (rise edge)5.005.00
clock network delay (ideal)0.205.20
clock uncertainty-0.015.19
output external delay-0.504.69
data required time4.69
-----------------------------------------------------------
data required time4.69
data arrival time-0.20
-----------------------------------------------------------
slack (MET)4.49


2、
Operating Conditions: NCCOMLibrary: tpz973gtc
Wire Load Model Mode: top
Startpoint: reset (input port)
Endpoint: dataout_reg[9]
(rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min
Des/Clust/PortWire Load ModelLibrary
------------------------------------------------
multiplierTSMC128K_Conservative tpz973gtc
PointIncrPath
-----------------------------------------------------------
clock (input port clock) (rise edge)0.000.00
clock network delay (ideal)0.000.00
input external delay0.000.00 f
reset (in)0.000.00 f
U3/Y (CLKINVX1)0.000.00 r
dataout_reg[9]/U2/Y (AND2X1)0.000.00 r
dataout_reg[9]/D (DFFHQX1)0.000.00 r
data arrival time0.00
clock clk (rise edge)0.000.00
clock network delay (ideal)0.100.10
clock uncertainty0.010.11
dataout_reg[9]/CK (DFFHQX1)0.000.11 r
library hold time0.000.11
data required time0.11
-----------------------------------------------------------
data required time0.11
data arrival time0.00
-----------------------------------------------------------
slack (VIOLATED)-0.11
我再贴下我用的2个库啊:typical.lib:
cell (ADDFHX2) {
cell_footprint : addfh;
area : 113.0976;
pin(A) {
direction : input;
capacitance : 0.01159;
}
pin(B) {
direction : input;
capacitance : 0.02595;
}
pin(CI) {
direction : input;
capacitance : 0.00805;
}
pin(S) {
direction : output;
capacitance : 0.0;
function : "(A ^ B ^ CI)";
internal_power() {
related_pin : "A";
when : "!B & !CI";
rise_power(energy_template_7x7) {
index_1 ("0.0300, 0.1000, 0.4000, 0.9000, 1.5000, 2.2000, 3.0000");
index_2 ("0.00070, 0.04200, 0.07700, 0.16800, 0.29400, 0.46200, 0.62300");
values ( \
"0.1774, 0.1829, 0.1818, 0.1792, 0.1754, 0.1701, 0.1645", \
"0.1753, 0.1812, 0.1801, 0.1774, 0.1734, 0.1681, 0.1635", \
"0.1869, 0.1919, 0.1908, 0.1882, 0.1844, 0.1791, 0.1735", \
"0.2259, 0.2239, 0.2221, 0.2188, 0.2144, 0.2091, 0.2045", \
"0.2712, 0.2700, 0.2676, 0.2651, 0.2614, 0.2561, 0.2505", \
"0.3256, 0.3251, 0.3252, 0.3202, 0.3164, 0.3111, 0.3055", \
"0.3900, 0.3899, 0.3901, 0.3881, 0.3814, 0.3761, 0.3705");
}

查找表看的,cell delay都是有的啊,求大神指点一下!感激不尽

谁来帮我回答一下啊?cell delay都是零,hold没有办法满足啊`

可否用report_delay_calculation -from -to 看得详细一点

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