ICC 报告的IO PAD延时为负值，何解？

输入transition设置的是1，load值也正常，ICC算得的延时却是-0.7，lib文件中没有负值。

问题不是很清楚

http://bbs.eetop.cn/thread-422693-1-1.html
和上面链接里的问题有点类似，等待大侠们解答

xtalk?

Hi
Negative net delays can result from any of the following:
voltage scaling
threshold scaling
crosstalk delay effects
derating
abstraction error

论坛里有这方面的参考资料吗?确实没太想明白
假设voltage scaling，怎么导致或者算出负值的 ，举个简单的例子说明一下

Threshold Scaling

Example:

driver delay threshold: 50%load delay threshold: 25%transition time 0% - 100% (ideal ramp) : 1.00nsnet delay : 0.10nsdriver pin: delay threshold of 50% VDD is reached after 0.5 nsload pin: delay threshold of 30% VDD is reached after 0.1ns (net delay) + 0.25ns = 0.35nsreported net delay : 0.35ns - 0.5ns = -0.15ns

With a short net and a long transition time, the 25% threshold at the load pin is reached earlier than the 50% threshold at the driver pin. The measured delay time between 25% and 50% is negative.

Voltage Scaling

driver delay threshold: 50%driver supply voltage : 3.0V => absolute threshold : 1.50Vload delay threshold: 50%load supply voltage: 1.5V => absolute threshold : 0.75Vtransition time 0% - 100% of 3.0V (ideal ramp) : 1.00nsramp starting at 0ns at driver pindriver pin: delay threshold of 1.50V is reached after 0.50nsnet delay : 0.10nsload pin: 1.50V is reached after 0.50ns + 0.10ns = 0.60ns=> delay threshold of 0.75V is reached after 0.25ns + 0.10ns = 0.35nsreported net delay : 0.35ns - 0.50ns = -0.15ns
Crosstalk Delay Effects PointDTransTransDeltaIncrPath-----------------------------------------------------------------------------inst_top/u2661/Z (ND4)0.080.20 &2.60 rinst_top/u2662/B (OR2)0.000.08-0.10-0.08 &2.52 rStage delay (cell + net): 0.20 - 0.08 = 0.12

Derating

set_timing_derate -early 0.75net delay (without crosstalk): 0.200nsstage delta delay: -0.184ns2003.12: (0.200ns - 0.184ns) * 0.75 = 0.012ns2004.06: (0.200ns * 0.75) + (-0.184ns * 1.25) = -0.08ns

谢谢

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