关于双端口RAM做STA疑问

设计当中使用了异步FIFO,FIFO内含有双端口RAM,做STA的时候发现PT并没有RAM的CLKA/CLKB当成时钟端口,而是直接计算了从时钟源到CLKA的延时大小然后相对于CLKB做setup检查,同样把两者的位置调换后又做了一次这样的检查.
有什么办法没有把RAM设置成具有时序单元的属性,让PT检查的时候将RAM的CLKA/CLKB当成时钟端口.
谢谢了

没有做过类似设计，不过有个疑问哈．
你希望ＰＴ不会把clka和clkb看成是时钟端口是为了算哪个timing　arc呢?
会不会dual　port　ram的db里面，就没有这个timing　arc呢?不然他一定会检查的吧．

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