DC综合时出现 1 high-fanout nets
时间：10-02
整理：3721RD
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做DC综合时出现 1 high-fanout nets，如下：
Warning: Design 'VR_CS_TOP' contains 1 high-fanout nets. A fanout number of 1000 will be used for delay calculations involving these nets. (TIM-134)
Net 'uVR_CS_DITHER/rstb': 1074 load(s), 1 driver(s)
"rstb"是复位信号，脚本设置如下：
create_clock -name pclk -period 30 -waveform [list 0 15] [get_ports pclk]
set_dont_touch_network [list pclk]
set_ideal_network -no_propagaterstb
set_disable_timing [get_ports rstb]
求高手赐教，谢谢！
Warning: Design 'VR_CS_TOP' contains 1 high-fanout nets. A fanout number of 1000 will be used for delay calculations involving these nets. (TIM-134)
Net 'uVR_CS_DITHER/rstb': 1074 load(s), 1 driver(s)
"rstb"是复位信号，脚本设置如下：
create_clock -name pclk -period 30 -waveform [list 0 15] [get_ports pclk]
set_dont_touch_network [list pclk]
set_ideal_network -no_propagaterstb
set_disable_timing [get_ports rstb]
求高手赐教，谢谢！
自顶，在线等
Dont care at DC.
Fix high fanout net at PR
I'll have a try.Thank you！