setup的fall_edge和rise_edge违例问题,不明白

在一个setup path中
Startpoint: jtag_INSTRUCTION_prog_spi_r_reg
(falling edge-triggered flip-flop clocked by tck)
Endpoint: jtag_REGISTER_bypass_r_reg
(rising edge-triggered flip-flop clocked by tck)
Path Group: tck
Path Type: max
------------------------------------------------------------------------------
clock tck (fall edge)20.0020.00
clock network delay (propagated)0.6520.65
jtag_INSTRUCTION_prog_spi_r_reg/CKB (DFCRM8NA)0.0020.65 f
jtag_INSTRUCTION_prog_spi_r_reg/Q (DFCRM8NA)0.12 &20.77 f
FE_PHC4394_n75658/Z (CKBUFM1N)0.07 &20.85 f
FE_PHC4393_n75658/Z (CKBUFM1N)0.07 &20.91 f
FE_PHC4392_n75658/Z (CKBUFM1N)0.07 &20.98 f
FE_PHC4391_n75658/Z (CKBUFM1N)0.08 &21.06 f
FE_PHC4390_n75658/Z (CKBUFM1N)0.08 &21.14 f
FE_PHC4389_n75658/Z (CKBUFM1N)0.07 &21.21 f
FE_PHC4388_n75658/Z (CKBUFM1N)0.08 &21.29 f
FE_PHC4395_n75658/Z (CKBUFM1N)0.06 &21.35 f
FE_PHC4296_n75658/Z (DEL4M4N)0.17 &21.53 f
FE_PHC4396_n75658/Z (BUFM3N)0.06 &21.58 f
FE_OFCC4612_FE_PHN3500_n75658/Z (BUFM6N)0.07 &21.65 f
.
.
.
中间省略200多个buffer或del
data arrival time59.47

clock tck (rise edge)40.0040.00
clock network delay (propagated)0.7340.73
jtag_REGISTER_bypass_r_reg/CK (DFQRM1NA)40.73 r
library setup time0.0340.76
data required time40.76
------------------------------------------------------------------------------
data required time40.76
data arrival time-59.47
------------------------------------------------------------------------------
slack (VIOLATED)-18.72
中间为什么会加那么多buffer呀?
违例那么大?
求高手们不吝赐教啊
在线等.....

应该是fanout太大以及驱动的问题，所以要加入好几级buf

能否发详细report，不要省略，连你的endpoint都看不到，表头没有不知道你的timing path

这个好像是属于上下沿与下降沿的问题，我还没搞明白

是不是扫描链修hold时插入太多 delay 单元了， 扫描链重组一下试试?