如何让ICC如何根据数据流来布局

这个难度很大，基本很难实现。
有所谓的module placement，可以部分。

用create bounds 可以让一部分std_cell的强制布局在某个区域，这个就不知道hold timing好不好修复。

hold time 一般不会有啥问题吧。
除非设置了太大的uncertainty.
建议可做OCV分析。

帅哥，他们说congestion GRC超过2%就不行，你帮我看看这个overflow报告。initial周期 超过了2% 但是phase1周期低于2% 那个是正解?
Start GR phase 0
Current Stage stats:
[End of Initial Routing] Elapsed real time: 0:00:00
[End of Initial Routing] Elapsed cputime: sys=0:00:00 usr=0:00:00 total=0:00:00
[End of Initial Routing] Stage (MB): Used2Alloctr2Proc0
[End of Initial Routing] Total (MB): Used13Alloctr14Proc541
Initial. Routing result:
Initial. Both Dirs: Overflow =325 Max = 4 GRCs =287 (3.29%)
Initial. H routing: Overflow =172 Max = 4 (GRCs =2) GRCs =149 (3.42%)
Initial. V routing: Overflow =152 Max = 4 (GRCs =3) GRCs =138 (3.17%)
Initial. M1Overflow =131 Max = 4 (GRCs =1) GRCs =108 (2.48%)
Initial. M2Overflow =151 Max = 4 (GRCs =3) GRCs =122 (2.80%)
Initial. M3Overflow =41 Max = 4 (GRCs =1) GRCs =41 (0.94%)
Initial. MTOverflow =1 Max = 0 (GRCs = 16) GRCs =16 (0.37%)
Initial. AMOverflow =0 Max = 0 (GRCs =0) GRCs =0 (0.00%)
Initial. Total Wire Length = 585316.75
Initial. Layer M1 wire length = 101658.99
Initial. Layer M2 wire length = 303137.09
Initial. Layer M3 wire length = 162600.70
Initial. Layer MT wire length = 17919.92
Initial. Layer AM wire length = 0.00
Initial. Total Number of Contacts = 28629
Initial. Via M1_M2_THICK_R count = 19679
Initial. Via M2_M3_THICK_R count = 8699
Initial. Via M3_MT_THICK_R count = 251
Initial. Via MT_AM_TS count = 0
Initial. completed.
Start GR phase 1
Current Stage stats:
[End of Phase1 Routing] Elapsed real time: 0:00:00
[End of Phase1 Routing] Elapsed cputime: sys=0:00:00 usr=0:00:00 total=0:00:00
[End of Phase1 Routing] Stage (MB): Used0Alloctr0Proc0
[End of Phase1 Routing] Total (MB): Used13Alloctr14Proc541
phase1. Routing result:
phase1. Both Dirs: Overflow =108 Max = 4 GRCs =84 (0.96%)
phase1. H routing: Overflow =29 Max = 4 (GRCs =1) GRCs =22 (0.51%)
phase1. V routing: Overflow =79 Max = 4 (GRCs =1) GRCs =62 (1.42%)
phase1. M1Overflow =29 Max = 4 (GRCs =1) GRCs =20 (0.46%)
phase1. M2Overflow =79 Max = 4 (GRCs =1) GRCs =61 (1.40%)
phase1. M3Overflow =0 Max = 0 (GRCs =2) GRCs =2 (0.05%)
phase1. MTOverflow =0 Max = 0 (GRCs =1) GRCs =1 (0.02%)
phase1. AMOverflow =0 Max = 0 (GRCs =0) GRCs =0 (0.00%)

all GRC results are correct. it will change in different stage.

陈总，那我在第一个步骤中GRC超过2% ，是否代表我阻塞比较严重，需要重新布局（place_opt -congestion），以作调整，还是参考第二步的数据不做不需要大的改变，谢谢！

以最后的GRC结果为准
那个根据数据流来布局，以前有过，大家反映不热烈，EDA厂家就把它丢了（一些有用的放到place里面了），现在一般的做法是，摆放RAM macro时，按照数据流的方向和位置摆，这样可以引导place 标准单元时也按照这个顺序

OK,谢谢陈总。

还可以写个程序手动place。
从report 看,CONGESTION 不是问题。

turn on hierarchy gravity and set effort high is good for your design data flow