synthesis problem

TSMC 90nm SRAM has signal EMA[2:0], when i use SRAM, i set EMA=3'b000,
===========================================================
SRAM_DP_ADV SRAM_i0 (
.CLKA(CLKA),
.CENA(CENA_n),
.WENA(WENA_n),
.QA(QA_n),
.DA(DA_n),
.AA({3'b000,AA_n}),
.EMAA(3'b000),
.CLKB(CLKB),
.CENB(CENB_n),
.WENB(WENB_n),
.QB(QB_n),
.DB(DB_n),
.AB({3'b000,AB_n}),
.EMAB(3'b000)
) ;
==============================
according to lib file, when reading SRAM, address to valid read-data is about 1.6,
bus(QA){
bus_type : SRAM_DP_ADV_DATA;
direction : output;
max_capacitance : 0.360;
memory_read() {
address : AA;
}
timing() {
related_pin :"CLKA" ;
timing_type : rising_edge;
timing_sense : non_unate;
when : "(！EMAA[2]) & (！EMAA[1]) & (！EMAA[0])";
sdf_cond : "EMAA[2] == 1'b0 && EMAA[1] == 1'b0 && EMAA[0] == 1'b0";
cell_rise(SRAM_DP_ADV_mem_out_delay_template) {
index_1 ("0.041, 0.067, 0.096, 0.155, 0.329, 0.619, 1.000");
index_2 ("0.001, 0.012, 0.024, 0.048, 0.120, 0.240, 0.360");
values ( \
"1.676, 1.686, 1.698, 1.720, 1.788, 1.901, 2.014", \
"1.677, 1.687, 1.698, 1.721, 1.789, 1.902, 2.015", \
"1.678, 1.688, 1.699, 1.722, 1.790, 1.903, 2.016", \
"1.680, 1.690, 1.701, 1.724, 1.792, 1.905, 2.018", \
"1.685, 1.696, 1.707, 1.729, 1.797, 1.910, 2.023", \
"1.695, 1.705, 1.716, 1.739, 1.807, 1.920, 2.033", \
"1.707, 1.717, 1.729, 1.751, 1.819, 1.932, 2.045" \
)
====================================================
but dc synthesis report show:
PointIncrPath
--------------------------------------------------------------------------
clock CLK (rise edge)0.000.00
clock network delay (ideal)0.000.00
tposemem/Bisted_DPR64x16/WRAPPED_RAM_i0/SRAM_i0/CLKA (SRAM_DP_ADV)
0.000.00 r
tposemem/Bisted_DPR64x16/WRAPPED_RAM_i0/SRAM_i0/QA[5] (SRAM_DP_ADV)
999.00999.00 r
====================================================
I guess when synthesis, dc choose the worst sdf_condition
timing() {
related_pin :"CLKA" ;
timing_type : rising_edge;
timing_sense : non_unate;
when : "(EMAA[2]) & (！EMAA[1]) & (！EMAA[0])";
sdf_cond : "EMAA[2] == 1'b1 && EMAA[1] == 1'b0 && EMAA[0] == 1'b0";
cell_rise(SRAM_DP_ADV_mem_out_delay_template) {
index_1 ("0.041, 0.067, 0.096, 0.155, 0.329, 0.619, 1.000");
index_2 ("0.001, 0.012, 0.024, 0.048, 0.120, 0.240, 0.360");
values ( \
"999.000, 999.000, 999.000, 999.000, 999.000, 999.000, 999.000", \
"999.000, 999.000, 999.000, 999.000, 999.000, 999.000, 999.000", \
"999.000, 999.000, 999.000, 999.000, 999.000, 999.000, 999.000", \
"999.000, 999.000, 999.000, 999.000, 999.000, 999.000, 999.000", \
"999.000, 999.000, 999.000, 999.000, 999.000, 999.000, 999.000", \
"999.000, 999.000, 999.000, 999.000, 999.000, 999.000, 999.000", \
"999.000, 999.000, 999.000, 999.000, 999.000, 999.000, 999.000" \
)
====================================================
how to solve it

在报告里看看net的load是不是太大

设置下 high_fanout相关参数

EMA 的设置有特殊讲究的，看前面的帖子，