如何从PT的STA report中看出RC delay的信息呢?
时间:10-02
整理:3721RD
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大大, pre-layout 和 post-layout阶段的PT STA report 描述delay的部分都是“Clock path delay” 和 “data path delay”, 哪里看得出RC delay 呢?
Example:
Reference arrival time
+ Cycle
-Setup
-----------------------------------
End-of-path required time (ps)
Starting arrival time
+ Clock path delay
+ Data path delay
-----------------------------------
End-of-path arrival time (ps)
Example:
Reference arrival time
+ Cycle
-Setup
-----------------------------------
End-of-path required time (ps)
Starting arrival time
+ Clock path delay
+ Data path delay
-----------------------------------
End-of-path arrival time (ps)
report_delay_calculation
感谢大大, 我的意思是说STA得出的report中总该RC delay, data path总不能仅仅是cell部分的吧? 如下面这个例子。“delay”出现"0"的地方不能理解啊。
Data path
pin namemodel namedelayAT
-----------------------------------------------------------------------
sa30_reg[7]/QSDFFX210823477
............
C10433/AXOR2XL1910190
C10433/YXOR2XL91811108
C10436_3/BXOR2XL011108
C10436_3/YXOR2XL53911674
C10436_4/AXOR2XL011648
C10436_4/YXOR2XL29111939
sa11_reg[1]/SISDFFX2011939
0就不是这段wire的delay可以忽略不计
下面的就是wire delay
C10433/AXOR2XL1910190