请教CALIBRE LVS Instance问题
时间：10-02
整理：3721RD
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小弟新手，想请教各位大神一个LVS的问题。我现在把一个标准单元库里一个单元的schematic和layout一起另存到一个地方，想在这个单元的基础上构建一个新的单元。但是我直接做LVS检查时(什么都还没改)layout里的管子都被认为是pepm或nenm，单元库里并没有这些管子，而且这些管子都被认为是一个instance了，schematic里用的enm和epm管子是库里有的，于是instance就不匹配了。我还没有改过这个单元，请问layout里的管子为什么会被认为是pepm或nenm呢?该怎样让instance匹配呢?
万分感谢！附上netlist和LVS Report。
Layout Netlist
* SPICE NETLIST
***************************************
.SUBCKT probe TERM1
.ENDS
***************************************
.SUBCKT thru TERM1 TERM2
.ENDS
***************************************
.SUBCKT v12 TERM1
.ENDS
***************************************
.SUBCKT v20 TERM1
.ENDS
***************************************
.SUBCKT v40 TERM1
.ENDS
***************************************
.SUBCKT ext TERM1
.ENDS
***************************************
.SUBCKT anmvhb G SD B
.ENDS
***************************************
.SUBCKT enmesq G D S B NW
.ENDS
***************************************
.SUBCKT schd PLUS MINUS SUBSTRATE
.ENDS
***************************************
.SUBCKT LDD G S D B
.ENDS
***************************************
.SUBCKT LDDN G S D B
.ENDS
***************************************
.SUBCKT LDDP G S D B
.ENDS
***************************************
.SUBCKT br02_b LVDD LVSS Q SUB A
** N=6 EP=5 IP=0 FDC=6
M0 LVSS A 2 SUB nenm L=6e-07 W=7.8e-06 $X=1650 $Y=2400 $D=77
M1 Q 2 LVSS SUB nenm L=6e-07 W=7.8e-06 $X=3550 $Y=2400 $D=77
M2 LVSS 2 Q SUB nenm L=6e-07 W=7.8e-06 $X=5450 $Y=2400 $D=77
M3 LVDD A 2 LVDD pepm L=6e-07 W=1.02e-05 $X=1650 $Y=16900 $D=78
M4 Q 2 LVDD LVDD pepm L=6e-07 W=1.02e-05 $X=3550 $Y=16900 $D=78
M5 LVDD 2 Q LVDD pepm L=6e-07 W=1.02e-05 $X=5450 $Y=16900 $D=78
.ENDS
***************************************
Source Netlist
************************************************************************
* auCdl Netlist:
*
* Library Name:test
* Top Cell Name: br02_b
* View Name:schematic
* Netlisted on:May8 15:52:45 2015
************************************************************************
*.EQUATION
*.SCALE METER
*.MEGA
.PARAM
*.GLOBAL vss！
+sub！
+vdd！
*.PIN vss！
*+sub！
*+vdd！
************************************************************************
* Library Name: test
* Cell Name:br02_b
* View Name:schematic
************************************************************************
.SUBCKT br02_b A Q
*.PININFO A:I Q:O
MNMOS_1 net4 A vss！ sub！ enm W=7.8 L=600e-3 m=1
MNMOS_2 Q net4 vss！ sub！ enm W=15.6 L=600e-3 m=1
MPMOS_1 net4 A vdd！ vdd！ epm W=10.2 L=600e-3 m=1
MPMOS_2 Q net4 vdd！ vdd！ epm W=20.4 L=600e-3 m=1
.ENDS
CALIBRE LVS Report
OVERALL COMPARISON RESULTS
#######################
# ###
##INCORRECT#
# ###
#######################
Error:Different numbers of nets.
Error:Different numbers of instances.
Error:Connectivity errors.
**************************************************************************************************************
CELLSUMMARY
**************************************************************************************************************
ResultLayoutSource
------------------------------------
INCORRECTbr02_bbr02_b
**************************************************************************************************************
LVS PARAMETERS
**************************************************************************************************************
o LVS Setup:
// LVS COMPONENT TYPE PROPERTY
// LVS COMPONENT SUBTYPE PROPERTY
// LVS PIN NAME PROPERTY
LVS POWER NAME"LVCC" "LVDD" "AVDD" "VCC" "VDD" "PS" "vdd！"
LVS GROUND NAME"LVSS" "AVSS" "ASUB" "SUB" "VSS" "GND" "NS" "gnd！" "sub！"
LVS CELL SUPPLYNO
LVS RECOGNIZE GATESALL
LVS IGNORE PORTSNO
LVS CHECK PORT NAMESYES
LVS IGNORE TRIVIAL NAMED PORTSNO
LVS BUILTIN DEVICE PIN SWAPYES
LVS ALL CAPACITOR PINS SWAPPABLENO
LVS DISCARD PINS BY DEVICENO
LVS SOFT SUBSTRATE PINSNO
LVS INJECT LOGICYES
LVS EXPAND UNBALANCED CELLSYES
LVS FLATTEN INSIDE CELLNO
LVS EXPAND SEED PROMOTIONSNO
LVS PRESERVE PARAMETERIZED CELLSNO
LVS GLOBALS ARE PORTSYES
LVS REVERSE WLNO
LVS SPICE PREFER PINSYES
LVS SPICE SLASH IS SPACEYES
LVS SPICE ALLOW FLOATING PINSYES
// LVS SPICE ALLOW INLINE PARAMETERS
LVS SPICE ALLOW UNQUOTED STRINGSYES
LVS SPICE CONDITIONAL LDDNO
LVS SPICE CULL PRIMITIVE SUBCIRCUITSNO
LVS SPICE IMPLIED MOS AREANO
// LVS SPICE MULTIPLIER NAME
LVS SPICE OVERRIDE GLOBALSNO
LVS SPICE REDEFINE PARAMNO
LVS SPICE REPLICATE DEVICESNO
LVS SPICE SCALE X PARAMETERSNO
LVS SPICE STRICT WLNO
// LVS SPICE OPTION
LVS STRICT SUBTYPESYES
LVS EXACT SUBTYPESNO
LAYOUT CASEYES
SOURCE CASEYES
LVS COMPARE CASENAMES TYPES SUBTYPES VALUES
LVS DOWNCASE DEVICENO
LVS REPORT MAXIMUM50
LVS PROPERTY RESOLUTION MAXIMUM32
// LVS SIGNATURE MAXIMUM
// LVS FILTER UNUSED OPTION
// LVS REPORT OPTION
LVS REPORT UNITSYES
// LVS NON USER NAME PORT
// LVS NON USER NAME NET
// LVS NON USER NAME INSTANCE
// Reduction
LVS REDUCE SERIES MOSYES
LVS REDUCE PARALLEL MOSYES
LVS REDUCE SEMI SERIES MOSNO
LVS REDUCE SPLIT GATESYES
LVS REDUCE PARALLEL BIPOLARYES
LVS REDUCE SERIES CAPACITORSYES
LVS REDUCE PARALLEL CAPACITORSYES
LVS REDUCE SERIES RESISTORSYES
LVS REDUCE PARALLEL RESISTORSYES
LVS REDUCE PARALLEL DIODESYES
LVS REDUCECPARALLEL
LVS REDUCEC(anmv)PARALLEL
LVS REDUCEC(apmv)PARALLEL
LVS REDUCEC(pipcnm)PARALLEL
LVS REDUCEC(pipcpm)PARALLEL
LVS REDUCEschdPARALLEL NO
LVS REDUCEschdSERIES PLUS MINUS NO
LVS REDUCEenmesqPARALLEL NO
LVS REDUCEenmesqSERIES S D NO
LVS REDUCEthruPARALLEL
LVS REDUCEthruSERIES TERM1 TERM2
LVS REDUCEprobePARALLEL
LVS REDUCEextPARALLEL
LVS REDUCEv5PARALLEL
LVS REDUCEv12PARALLEL
LVS REDUCEv20PARALLEL
LVS REDUCEv40PARALLEL
LVS REDUCTION PRIORITYPARALLEL
LVS SHORT EQUIVALENT NODESNO
// Filter
LVS FILTERD(ppnwd)OPEN
LVS FILTERD(nppwd)OPEN
LVS FILTERD(nwpsubd)OPEN
// Trace Property
TRACE PROPERTYqa a 0.1
TRACE PROPERTYca area 0.1
TRACE PROPERTYcp peri 0.1
TRACE PROPERTYc(anmv)l l 0.1
TRACE PROPERTYc(anmv)w w 0.1
TRACE PROPERTYc(apmv)l l 0.1
TRACE PROPERTYc(apmv)w w 0.1
TRACE PROPERTYc(pipcnm)l l 0.1
TRACE PROPERTYc(pipcnm)w w 0.1
TRACE PROPERTYc(pipcpm)l l 0.1
TRACE PROPERTYc(pipcpm)w w 0.1
TRACE PROPERTYrl l 0.1
TRACE PROPERTYrw w 0.1
TRACE PROPERTYda a 0.1
TRACE PROPERTYdp peri 0.1
TRACE PROPERTYml l 0.1
TRACE PROPERTYmw w 0.1
TRACE PROPERTYmnl l 0.1
TRACE PROPERTYmnw w 0.1
TRACE PROPERTYmpl l 0.1
TRACE PROPERTYmpw w 0.1
TRACE PROPERTYlddl l 0.1
TRACE PROPERTYlddw w 0.1
TRACE PROPERTYlddnl l 0.1
TRACE PROPERTYlddnw w 0.1
TRACE PROPERTYlddpl l 0.1
TRACE PROPERTYlddpw w 0.1
CELL COMPARISON RESULTS ( TOP LEVEL )
#######################
# ###
##INCORRECT#
# ###
#######################
Error:Different numbers of nets (see below).
Error:Different numbers of instances (see below).
Error:Connectivity errors.
LAYOUT CELL NAME:br02_b
SOURCE CELL NAME:br02_b
--------------------------------------------------------------------------------------------------------------
INITIAL NUMBERS OF OBJECTS
--------------------------
LayoutSourceComponent Type
--------------------------
Ports:55
Nets:66
Instances:04*ME (4 pins)
30*MN (4 pins)
30*MP (4 pins)
------------
Total Inst:64
NUMBERS OF OBJECTS AFTER TRANSFORMATION
---------------------------------------
LayoutSourceComponent Type
--------------------------
Ports:55
Nets:56*
Instances:04*ME (4 pins)
10*_invx2b (6 pins)
------------
Total Inst:14
* = Number of objects in layout different from number in source.
**************************************************************************************************************
INCORRECT OBJECTS
**************************************************************************************************************
LEGEND:
-------
ne= Naming Error (same layout name found in source
circuit, but object was matched otherwise).
**************************************************************************************************************
INCORRECT NETS
DISC#LAYOUT NAMESOURCE NAME
**************************************************************************************************************
1Net LVDD** no similar net **
--------------------------------------------------------------------------------------------------------------
2Net LVSS** no similar net **
--------------------------------------------------------------------------------------------------------------
3Net SUB** no similar net **
--------------------------------------------------------------------------------------------------------------
4** no similar net **sub！
--------------------------------------------------------------------------------------------------------------
5** no similar net **net4
--------------------------------------------------------------------------------------------------------------
6** no similar net **vss！
--------------------------------------------------------------------------------------------------------------
7** no similar net **vdd！
**************************************************************************************************************
INCORRECT INSTANCES
DISC#LAYOUT NAMESOURCE NAME
**************************************************************************************************************
8(_invx2b)** missing injected instance **
Devices:
M3(1.650,16.900)MP(pepm)
M0(1.650,2.400)MN(nenm)
M5(5.450,16.900)MP(pepm)
M2(5.450,2.400)MN(nenm)
--------------------------------------------------------------------------------------------------------------
9** missing instance **MNMOS_1ME(enm)
--------------------------------------------------------------------------------------------------------------
10** missing instance **MNMOS_2ME(enm)
--------------------------------------------------------------------------------------------------------------
11** missing instance **MPMOS_1ME(epm)
--------------------------------------------------------------------------------------------------------------
12** missing instance **MPMOS_2ME(epm)
**************************************************************************************************************
INFORMATION AND WARNINGS
**************************************************************************************************************
MatchedMatchedUnmatchedUnmatchedComponent
LayoutSourceLayoutSourceType
-----------------------------------------
Ports:2233
Nets:2234
Instances:0002ME(enm)
0002ME(epm)
0010_invx2b
--------------------------------
Total Inst:0014
o Statistics:
4 layout mos transistors were reduced to 2.
2 mos transistors were deleted by parallel reduction.
o Layout Names That Are Missing In The Source:
Ports:LVDD LVSS SUB
Nets:LVDD LVSS SUB
o Initial Correspondence Points:
Ports:Q A
**************************************************************************************************************
UNMATCHED OBJECTS
LAYOUTSOURCE
**************************************************************************************************************
LVDD on net: LVDD** unmatched port **
LVSS on net: LVSS** unmatched port **
SUB on net: SUB** unmatched port **
** unmatched net **vdd！
** unmatched port **vdd！ on net: vdd！
** unmatched port **sub！ on net: sub！
** unmatched port **vss！ on net: vss！
**************************************************************************************************************
SUMMARY
**************************************************************************************************************
Total CPU Time:0 sec
Total Elapsed Time:0 sec
万分感谢！附上netlist和LVS Report。
Layout Netlist
* SPICE NETLIST
***************************************
.SUBCKT probe TERM1
.ENDS
***************************************
.SUBCKT thru TERM1 TERM2
.ENDS
***************************************
.SUBCKT v12 TERM1
.ENDS
***************************************
.SUBCKT v20 TERM1
.ENDS
***************************************
.SUBCKT v40 TERM1
.ENDS
***************************************
.SUBCKT ext TERM1
.ENDS
***************************************
.SUBCKT anmvhb G SD B
.ENDS
***************************************
.SUBCKT enmesq G D S B NW
.ENDS
***************************************
.SUBCKT schd PLUS MINUS SUBSTRATE
.ENDS
***************************************
.SUBCKT LDD G S D B
.ENDS
***************************************
.SUBCKT LDDN G S D B
.ENDS
***************************************
.SUBCKT LDDP G S D B
.ENDS
***************************************
.SUBCKT br02_b LVDD LVSS Q SUB A
** N=6 EP=5 IP=0 FDC=6
M0 LVSS A 2 SUB nenm L=6e-07 W=7.8e-06 $X=1650 $Y=2400 $D=77
M1 Q 2 LVSS SUB nenm L=6e-07 W=7.8e-06 $X=3550 $Y=2400 $D=77
M2 LVSS 2 Q SUB nenm L=6e-07 W=7.8e-06 $X=5450 $Y=2400 $D=77
M3 LVDD A 2 LVDD pepm L=6e-07 W=1.02e-05 $X=1650 $Y=16900 $D=78
M4 Q 2 LVDD LVDD pepm L=6e-07 W=1.02e-05 $X=3550 $Y=16900 $D=78
M5 LVDD 2 Q LVDD pepm L=6e-07 W=1.02e-05 $X=5450 $Y=16900 $D=78
.ENDS
***************************************
Source Netlist
************************************************************************
* auCdl Netlist:
*
* Library Name:test
* Top Cell Name: br02_b
* View Name:schematic
* Netlisted on:May8 15:52:45 2015
************************************************************************
*.EQUATION
*.SCALE METER
*.MEGA
.PARAM
*.GLOBAL vss！
+sub！
+vdd！
*.PIN vss！
*+sub！
*+vdd！
************************************************************************
* Library Name: test
* Cell Name:br02_b
* View Name:schematic
************************************************************************
.SUBCKT br02_b A Q
*.PININFO A:I Q:O
MNMOS_1 net4 A vss！ sub！ enm W=7.8 L=600e-3 m=1
MNMOS_2 Q net4 vss！ sub！ enm W=15.6 L=600e-3 m=1
MPMOS_1 net4 A vdd！ vdd！ epm W=10.2 L=600e-3 m=1
MPMOS_2 Q net4 vdd！ vdd！ epm W=20.4 L=600e-3 m=1
.ENDS
CALIBRE LVS Report
OVERALL COMPARISON RESULTS
#######################
# ###
##INCORRECT#
# ###
#######################
Error:Different numbers of nets.
Error:Different numbers of instances.
Error:Connectivity errors.
**************************************************************************************************************
CELLSUMMARY
**************************************************************************************************************
ResultLayoutSource
------------------------------------
INCORRECTbr02_bbr02_b
**************************************************************************************************************
LVS PARAMETERS
**************************************************************************************************************
o LVS Setup:
// LVS COMPONENT TYPE PROPERTY
// LVS COMPONENT SUBTYPE PROPERTY
// LVS PIN NAME PROPERTY
LVS POWER NAME"LVCC" "LVDD" "AVDD" "VCC" "VDD" "PS" "vdd！"
LVS GROUND NAME"LVSS" "AVSS" "ASUB" "SUB" "VSS" "GND" "NS" "gnd！" "sub！"
LVS CELL SUPPLYNO
LVS RECOGNIZE GATESALL
LVS IGNORE PORTSNO
LVS CHECK PORT NAMESYES
LVS IGNORE TRIVIAL NAMED PORTSNO
LVS BUILTIN DEVICE PIN SWAPYES
LVS ALL CAPACITOR PINS SWAPPABLENO
LVS DISCARD PINS BY DEVICENO
LVS SOFT SUBSTRATE PINSNO
LVS INJECT LOGICYES
LVS EXPAND UNBALANCED CELLSYES
LVS FLATTEN INSIDE CELLNO
LVS EXPAND SEED PROMOTIONSNO
LVS PRESERVE PARAMETERIZED CELLSNO
LVS GLOBALS ARE PORTSYES
LVS REVERSE WLNO
LVS SPICE PREFER PINSYES
LVS SPICE SLASH IS SPACEYES
LVS SPICE ALLOW FLOATING PINSYES
// LVS SPICE ALLOW INLINE PARAMETERS
LVS SPICE ALLOW UNQUOTED STRINGSYES
LVS SPICE CONDITIONAL LDDNO
LVS SPICE CULL PRIMITIVE SUBCIRCUITSNO
LVS SPICE IMPLIED MOS AREANO
// LVS SPICE MULTIPLIER NAME
LVS SPICE OVERRIDE GLOBALSNO
LVS SPICE REDEFINE PARAMNO
LVS SPICE REPLICATE DEVICESNO
LVS SPICE SCALE X PARAMETERSNO
LVS SPICE STRICT WLNO
// LVS SPICE OPTION
LVS STRICT SUBTYPESYES
LVS EXACT SUBTYPESNO
LAYOUT CASEYES
SOURCE CASEYES
LVS COMPARE CASENAMES TYPES SUBTYPES VALUES
LVS DOWNCASE DEVICENO
LVS REPORT MAXIMUM50
LVS PROPERTY RESOLUTION MAXIMUM32
// LVS SIGNATURE MAXIMUM
// LVS FILTER UNUSED OPTION
// LVS REPORT OPTION
LVS REPORT UNITSYES
// LVS NON USER NAME PORT
// LVS NON USER NAME NET
// LVS NON USER NAME INSTANCE
// Reduction
LVS REDUCE SERIES MOSYES
LVS REDUCE PARALLEL MOSYES
LVS REDUCE SEMI SERIES MOSNO
LVS REDUCE SPLIT GATESYES
LVS REDUCE PARALLEL BIPOLARYES
LVS REDUCE SERIES CAPACITORSYES
LVS REDUCE PARALLEL CAPACITORSYES
LVS REDUCE SERIES RESISTORSYES
LVS REDUCE PARALLEL RESISTORSYES
LVS REDUCE PARALLEL DIODESYES
LVS REDUCECPARALLEL
LVS REDUCEC(anmv)PARALLEL
LVS REDUCEC(apmv)PARALLEL
LVS REDUCEC(pipcnm)PARALLEL
LVS REDUCEC(pipcpm)PARALLEL
LVS REDUCEschdPARALLEL NO
LVS REDUCEschdSERIES PLUS MINUS NO
LVS REDUCEenmesqPARALLEL NO
LVS REDUCEenmesqSERIES S D NO
LVS REDUCEthruPARALLEL
LVS REDUCEthruSERIES TERM1 TERM2
LVS REDUCEprobePARALLEL
LVS REDUCEextPARALLEL
LVS REDUCEv5PARALLEL
LVS REDUCEv12PARALLEL
LVS REDUCEv20PARALLEL
LVS REDUCEv40PARALLEL
LVS REDUCTION PRIORITYPARALLEL
LVS SHORT EQUIVALENT NODESNO
// Filter
LVS FILTERD(ppnwd)OPEN
LVS FILTERD(nppwd)OPEN
LVS FILTERD(nwpsubd)OPEN
// Trace Property
TRACE PROPERTYqa a 0.1
TRACE PROPERTYca area 0.1
TRACE PROPERTYcp peri 0.1
TRACE PROPERTYc(anmv)l l 0.1
TRACE PROPERTYc(anmv)w w 0.1
TRACE PROPERTYc(apmv)l l 0.1
TRACE PROPERTYc(apmv)w w 0.1
TRACE PROPERTYc(pipcnm)l l 0.1
TRACE PROPERTYc(pipcnm)w w 0.1
TRACE PROPERTYc(pipcpm)l l 0.1
TRACE PROPERTYc(pipcpm)w w 0.1
TRACE PROPERTYrl l 0.1
TRACE PROPERTYrw w 0.1
TRACE PROPERTYda a 0.1
TRACE PROPERTYdp peri 0.1
TRACE PROPERTYml l 0.1
TRACE PROPERTYmw w 0.1
TRACE PROPERTYmnl l 0.1
TRACE PROPERTYmnw w 0.1
TRACE PROPERTYmpl l 0.1
TRACE PROPERTYmpw w 0.1
TRACE PROPERTYlddl l 0.1
TRACE PROPERTYlddw w 0.1
TRACE PROPERTYlddnl l 0.1
TRACE PROPERTYlddnw w 0.1
TRACE PROPERTYlddpl l 0.1
TRACE PROPERTYlddpw w 0.1
CELL COMPARISON RESULTS ( TOP LEVEL )
#######################
# ###
##INCORRECT#
# ###
#######################
Error:Different numbers of nets (see below).
Error:Different numbers of instances (see below).
Error:Connectivity errors.
LAYOUT CELL NAME:br02_b
SOURCE CELL NAME:br02_b
--------------------------------------------------------------------------------------------------------------
INITIAL NUMBERS OF OBJECTS
--------------------------
LayoutSourceComponent Type
--------------------------
Ports:55
Nets:66
Instances:04*ME (4 pins)
30*MN (4 pins)
30*MP (4 pins)
------------
Total Inst:64
NUMBERS OF OBJECTS AFTER TRANSFORMATION
---------------------------------------
LayoutSourceComponent Type
--------------------------
Ports:55
Nets:56*
Instances:04*ME (4 pins)
10*_invx2b (6 pins)
------------
Total Inst:14
* = Number of objects in layout different from number in source.
**************************************************************************************************************
INCORRECT OBJECTS
**************************************************************************************************************
LEGEND:
-------
ne= Naming Error (same layout name found in source
circuit, but object was matched otherwise).
**************************************************************************************************************
INCORRECT NETS
DISC#LAYOUT NAMESOURCE NAME
**************************************************************************************************************
1Net LVDD** no similar net **
--------------------------------------------------------------------------------------------------------------
2Net LVSS** no similar net **
--------------------------------------------------------------------------------------------------------------
3Net SUB** no similar net **
--------------------------------------------------------------------------------------------------------------
4** no similar net **sub！
--------------------------------------------------------------------------------------------------------------
5** no similar net **net4
--------------------------------------------------------------------------------------------------------------
6** no similar net **vss！
--------------------------------------------------------------------------------------------------------------
7** no similar net **vdd！
**************************************************************************************************************
INCORRECT INSTANCES
DISC#LAYOUT NAMESOURCE NAME
**************************************************************************************************************
8(_invx2b)** missing injected instance **
Devices:
M3(1.650,16.900)MP(pepm)
M0(1.650,2.400)MN(nenm)
M5(5.450,16.900)MP(pepm)
M2(5.450,2.400)MN(nenm)
--------------------------------------------------------------------------------------------------------------
9** missing instance **MNMOS_1ME(enm)
--------------------------------------------------------------------------------------------------------------
10** missing instance **MNMOS_2ME(enm)
--------------------------------------------------------------------------------------------------------------
11** missing instance **MPMOS_1ME(epm)
--------------------------------------------------------------------------------------------------------------
12** missing instance **MPMOS_2ME(epm)
**************************************************************************************************************
INFORMATION AND WARNINGS
**************************************************************************************************************
MatchedMatchedUnmatchedUnmatchedComponent
LayoutSourceLayoutSourceType
-----------------------------------------
Ports:2233
Nets:2234
Instances:0002ME(enm)
0002ME(epm)
0010_invx2b
--------------------------------
Total Inst:0014
o Statistics:
4 layout mos transistors were reduced to 2.
2 mos transistors were deleted by parallel reduction.
o Layout Names That Are Missing In The Source:
Ports:LVDD LVSS SUB
Nets:LVDD LVSS SUB
o Initial Correspondence Points:
Ports:Q A
**************************************************************************************************************
UNMATCHED OBJECTS
LAYOUTSOURCE
**************************************************************************************************************
LVDD on net: LVDD** unmatched port **
LVSS on net: LVSS** unmatched port **
SUB on net: SUB** unmatched port **
** unmatched net **vdd！
** unmatched port **vdd！ on net: vdd！
** unmatched port **sub！ on net: sub！
** unmatched port **vss！ on net: vss！
**************************************************************************************************************
SUMMARY
**************************************************************************************************************
Total CPU Time:0 sec
Total Elapsed Time:0 sec
schematic里用的管子类型改成跟版图类型一样的就可以了
原始库里面的这个单元没有问题吗?
怎么没有人回答呢?我也遇到了相同的问题
看下rule里对于两类器件的定义。
先看一下command file相关的定义 在修改一下map文件