请教个关于verilog问题
时间：10-02
整理：3721RD
点击：
请教：下面的程序的 throughput 为什么是2.7bits/clock?谢谢
module powerv3(
output [7:0] XPower,
output
finished,
input [7:0] X,
input
clk,
input
start
);
reg [7:0] ncount;
reg [7:0] XPower1;
assign finished = (ncount == 0);
assign XPower = XPower1;
always@(posedge clk)
if(start)
begin
XPower1 <= X;
ncount <= 2;
end
else if(！finished)
begin
ncount <= ncount - 1;
XPower1 <= XPower1 * X;
end
endmodule
module powerv3(
output [7:0] XPower,
output
finished,
input [7:0] X,
input
clk,
input
start
);
reg [7:0] ncount;
reg [7:0] XPower1;
assign finished = (ncount == 0);
assign XPower = XPower1;
always@(posedge clk)
if(start)
begin
XPower1 <= X;
ncount <= 2;
end
else if(！finished)
begin
ncount <= ncount - 1;
XPower1 <= XPower1 * X;
end
endmodule
或者说，应该看重工艺中哪些最重要的参数
或者说，应该看重工艺中哪些最重要的参数