求助:除法器 仿真 出错
module divider_N(CLK_1M,A,B,C,D,RFD);
input CLK_1M;
input [15:0]A;
input [15:0]B;
output [15:0]C;
output [15:0]D;
output RFD;
//实例化除法器divide
divide U1 (
.clk(CLK_1M),
.dividend(A),
.divisor(B),
.quotient(C),
.remainder(Q),
.rfd(RFD));
endmodule
在用ISE自带的仿真工具进行仿真时,出现如下的error提示:
ERROR:HDLParsers:3482 - Could not resolve instantiated unit div_GEN_V1_0 in Verilog module work/divide in any library
ERROR:Simulator:198 - Failed when handling dependencies for module divider_N_tbw
功能仿真无法实现,请指教
通过查找,得到如下提示:
When running 9.1i ISE Simulator, all or some of the following errors are encountered:
"ERROR:HDLParsers:14 - Dependency database /hdpdeps.ref doesn't exist and can't be written"
"ERROR:HDLParsers:3482 - Could not resolve instantiated unit <name> in Verilog module work/<name> in any library"
"ERROR:Simulator:198 - Failed when handling dependencies for module <name>"
Solution 1:
This problem has been fixed in the latest 9.1i Service Pack available at:
http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is 9.1i Service Pack 1.
所以我就进入上面网站,下载了更新。但是我用的是ISE 8.2i,而下载来的更新是9.1i版本的,安装不上啊 !(好像不匹配)
怎么办?
这是因为你仿真的时候没有加入xiinx的库,你用xilinx的ip生成工具ipgenerator生成的ip在仿真时都必须加入xilinx的库才能仿真的。库就是这些ip的行为模型的verilog描叙。
怎么编译和加入库,可以在网上搜索:xilin 库编译 modelsim 仿真库 等关键词。
我用的是ISE自带的仿真工具,并且先前我曾经做过乘法器和累加器的仿真,功能仿真是可以出来的;
我在怀疑:是不是应该更新IP核?
点击ERROR提示,在官方网站上得到如下提示:
When running 9.1i ISE Simulator, all or some of the following errors are encountered:
"ERROR:HDLParsers:14 - Dependency database /hdpdeps.ref doesn't exist and can't be written"
"ERROR:HDLParsers:3482 - Could not resolve instantiated unit <name> in Verilog module work/<name> in any library"
"ERROR:Simulator:198 - Failed when handling dependencies for module <name>"
Solution 1:
This problem has been fixed in the latest 9.1i Service Pack available at:
http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is 9.1i Service Pack 1.
所以我就进入上面网站,下载了更新。但是我用的是ISE 8.2i,而下载来的更新是9.1i版本的,安装不上啊 !(好像不匹配)