时钟信号的切换

时钟信号的切换
Use clock gating. resynchronize the clock enable signal

时钟信号的切换
好问题，希望看到进一步的讨论！

时钟信号的切换
闲着没事，做个小例子，看看行不行?
用了四个同步器，可能比较笨笨，并测试了一下：
module clkswitch ( clkout, async_clk0, async_clk1, sel, rst_n);
output clkout;//输出时钟
inputasync_clk0;//输入异步时钟0
inputasync_clk1;//输入异步时钟1
inputsel;//选择端，0则选择时钟0，1则选择时钟1
inputrst_n;

wire sync_sel_clk0;
wire sync_sel_clk1;
wire clk0_g;
wire clk1_g;
wire handshake_f1t0;
wire handshake_f0t1;
wire clk0_gating;
wire clk1_gating;

//下面是同步器用的一堆reg
reglatch2_1;
reglatch1_1;
reglatch0_1;
reglatch2_0;
reglatch1_0;
reglatch0_0;

reghs_latch_f1_t0_2nd;
reghs_latch_f1_t0_1st;
reghs_latch_f0_t1_2nd;
reghs_latch_f0_t1_1st;

// 产生输出时钟的组合逻辑

assign sync_sel_clk1 = latch1_1;
assign sync_sel_clk0 = latch1_0;
assign handshake_f1t0 = hs_latch_f1_t0_2nd;
assign handshake_f0t1 = hs_latch_f0_t1_2nd;
assign clk0_g = clk0_gating & async_clk0;
assign clk0_gating = (~sync_sel_clk0) & (~handshake_f1t0);
assign clk1_g = clk1_gating & async_clk1;
assign clk1_gating = (sync_sel_clk1 & handshake_f0t1);
assign clkout = clk0_g | clk1_g;
// 在clk1域内同步sel
always @(posedge async_clk1 or negedge rst_n) begin
if (rst_n == 0) begin
latch2_1 <= 1'b0;
latch1_1 <= 1'b0;
latch0_1 <= 1'b0;
end
else begin
latch2_1 <= latch1_1;
latch1_1 <= latch0_1;
latch0_1 <= sel;
end
end
// 在clk0域内同步sel
always @(posedge async_clk0 or negedge rst_n) begin
if (rst_n == 0) begin
latch2_0 <= 0;
latch1_0 <= 0;
latch0_0 <= 0;
end
else begin
latch2_0 <= latch1_0;
latch1_0 <= latch0_0;
latch0_0 <= sel;
end
end
// 将clk1中同步后的sel送到clk0域内再同步一下

always @(posedge async_clk0 or negedge rst_n) begin
if (rst_n == 0) begin
hs_latch_f1_t0_2nd <= 0;
hs_latch_f1_t0_1st <= 0;
end
else begin
hs_latch_f1_t0_2nd <= hs_latch_f1_t0_1st;
hs_latch_f1_t0_1st <= latch2_1;
end
end
// 将clk0中同步后的sel送到clk1域内再同步一下
always @(posedge async_clk1 or negedge rst_n) begin
if (rst_n == 0) begin
hs_latch_f0_t1_2nd <= 0;
hs_latch_f0_t1_1st <= 0;
end
else begin
hs_latch_f0_t1_2nd <= hs_latch_f0_t1_1st;
hs_latch_f0_t1_1st <= latch2_0;
end

end

endmodule

谢谢小编，学学了！

想请教一下4楼的代码，为什么将clk1中同步后的sel送到clk0域内再同步的时候，要使用Latch2_1的输出而不能直接使用latch1_1的输出呢，就是想问为什么一定要用3级的寄存器采样sel而不能只用2级。
请各位高手指点，谢谢

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